From e1e54f3fbee6c0652e19182f4c747de172cbe8b1 Mon Sep 17 00:00:00 2001 From: Eduardo Habkost Date: Thu, 22 Nov 2012 13:31:03 -0200 Subject: [PATCH] target-i386: cpu: add missing flags to Haswell CPU model MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When adding the Haswell CPU model, I intended to make it a superset of the features present on the SandyBridge model, but I have removed the SEP and RDTSCP features from the feature list by mistake. This patch adds the missing SEP and RDTSCP features (that are present on SandyBridge) to Haswell. Reported-by: Martin Kletzander Acked-by: Andreas Färber Signed-off-by: Eduardo Habkost Signed-off-by: Anthony Liguori --- target-i386/cpu.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 64c34910a0..4fdd4f72d2 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -657,7 +657,7 @@ static x86_def_t builtin_x86_defs[] = { .stepping = 1, .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | - CPUID_PGE | CPUID_MTRR | CPUID_APIC | CPUID_CX8 | + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | CPUID_FP87, .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | @@ -666,7 +666,8 @@ static x86_def_t builtin_x86_defs[] = { CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | CPUID_EXT_PCID, - .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, + .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | + CPUID_EXT2_SYSCALL, .ext3_features = CPUID_EXT3_LAHF_LM, .cpuid_7_0_ebx_features = CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |