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tcg/aarch64: Use tcg_use_softmmu 

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
master
Richard Henderson 2023-10-01 16:26:53 +00:00
parent 2c53bdf110
commit e2b7a40d05
1 changed files with 88 additions and 89 deletions
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23
tcg/aarch64/tcg-target.c.inc
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@ -77,9 +77,7 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
#define TCG_REG_TMP2 TCG_REG_X30
#define TCG_VEC_TMP0 TCG_REG_V31
#ifndef CONFIG_SOFTMMU
#define TCG_REG_GUEST_BASE TCG_REG_X28
#endif
static bool reloc_pc26(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
{
@ -1664,7 +1662,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
s_bits == MO_128);
a_mask = (1 << h->aa.align) - 1;
#ifdef CONFIG_SOFTMMU
if (tcg_use_softmmu) {
unsigned s_mask = (1u << s_bits) - 1;
unsigned mem_index = get_mmuidx(oi);
TCGReg addr_adj;
@ -1690,10 +1688,10 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
TCG_REG_TMP0, TCG_REG_TMP0, addr_reg,
s->page_bits - CPU_TLB_ENTRY_BITS);
/* Add the tlb_table pointer, forming the CPUTLBEntry address in TMP1. */
/* Add the tlb_table pointer, forming the CPUTLBEntry address. */
tcg_out_insn(s, 3502, ADD, 1, TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_TMP0);
/* Load the tlb comparator into TMP0, and the fast path addend into TMP1. */
/* Load the tlb comparator into TMP0, and the fast path addend. */
QEMU_BUILD_BUG_ON(HOST_BIG_ENDIAN);
tcg_out_ld(s, addr_type, TCG_REG_TMP0, TCG_REG_TMP1,
is_ld ? offsetof(CPUTLBEntry, addr_read)
@ -1702,9 +1700,10 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
offsetof(CPUTLBEntry, addend));
/*
* For aligned accesses, we check the first byte and include the alignment
* bits within the address. For unaligned access, we check that we don't
* cross pages using the address of the last byte of the access.
* For aligned accesses, we check the first byte and include
* the alignment bits within the address. For unaligned access,
* we check that we don't cross pages using the address of the
* last byte of the access.
*/
if (a_mask >= s_mask) {
addr_adj = addr_reg;
@ -1729,7 +1728,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
h->base = TCG_REG_TMP1;
h->index = addr_reg;
h->index_ext = addr_type;
#else
} else {
if (a_mask) {
ldst = new_ldst_label(s);
@ -1754,7 +1753,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
h->index = TCG_REG_XZR;
h->index_ext = TCG_TYPE_I64;
}
#endif
}
return ldst;
}
@ -3117,7 +3116,7 @@ static void tcg_target_qemu_prologue(TCGContext *s)
tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE,
CPU_TEMP_BUF_NLONGS * sizeof(long));
#if !defined(CONFIG_SOFTMMU)
if (!tcg_use_softmmu) {
/*
* Note that XZR cannot be encoded in the address base register slot,
* as that actually encodes SP. Depending on the guest, we may need
@ -3126,7 +3125,7 @@ static void tcg_target_qemu_prologue(TCGContext *s)
*/
tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_GUEST_BASE, guest_base);
tcg_regset_set_reg(s->reserved_regs, TCG_REG_GUEST_BASE);
#endif
}
tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
tcg_out_insn(s, 3207, BR, tcg_target_call_iarg_regs[1]);