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hw/pxa2xx.c: Convert CLKCFG and PWRMODE cp14 regs 

Convert the PXA2xx CLKCFG and PWRMODE cp14 registers to the
new arm_cp_reginfo scheme.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
master
Peter Maydell 2012-06-20 11:57:07 +00:00
parent dc2a9045cf
commit e2f8a44d0d
1 changed files with 69 additions and 98 deletions
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83
hw/pxa2xx.c
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@ -224,43 +224,37 @@ static const VMStateDescription vmstate_pxa2xx_cm = {
} }
}; };
static uint32_t pxa2xx_clkpwr_read(void *opaque, int op2, int reg, int crm) static int pxa2xx_clkcfg_read(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t *value)
{ {
PXA2xxState *s = (PXA2xxState *) opaque; PXA2xxState *s = (PXA2xxState *)ri->opaque;
*value = s->clkcfg;
switch (reg) {
case 6: /* Clock Configuration register */
return s->clkcfg;
case 7: /* Power Mode register */
return 0; return 0;
}
default: static int pxa2xx_clkcfg_write(CPUARMState *env, const ARMCPRegInfo *ri,
printf("%s: Bad register 0x%x\n", __FUNCTION__, reg); uint64_t value)
break; {
PXA2xxState *s = (PXA2xxState *)ri->opaque;
s->clkcfg = value & 0xf;
if (value & 2) {
printf("%s: CPU frequency change attempt\n", __func__);
} }
return 0; return 0;
} }
static void pxa2xx_clkpwr_write(void *opaque, int op2, int reg, int crm, static int pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint32_t value) uint64_t value)
{ {
PXA2xxState *s = (PXA2xxState *) opaque; PXA2xxState *s = (PXA2xxState *)ri->opaque;
static const char *pwrmode[8] = { static const char *pwrmode[8] = {
"Normal", "Idle", "Deep-idle", "Standby", "Normal", "Idle", "Deep-idle", "Standby",
"Sleep", "reserved (!)", "reserved (!)", "Deep-sleep", "Sleep", "reserved (!)", "reserved (!)", "Deep-sleep",
}; };
switch (reg) { if (value & 8) {
case 6: /* Clock Configuration register */ printf("%s: CPU voltage change attempt\n", __func__);
s->clkcfg = value & 0xf; }
if (value & 2)
printf("%s: CPU frequency change attempt\n", __FUNCTION__);
break;
case 7: /* Power Mode register */
if (value & 8)
printf("%s: CPU voltage change attempt\n", __FUNCTION__);
switch (value & 7) { switch (value & 7) {
case 0: case 0:
/* Do nothing */ /* Do nothing */
@ -313,42 +307,13 @@ static void pxa2xx_clkpwr_write(void *opaque, int op2, int reg, int crm,
default: default:
message: message:
printf("%s: machine entered %s mode\n", __FUNCTION__, printf("%s: machine entered %s mode\n", __func__,
pwrmode[value & 7]); pwrmode[value & 7]);
} }
break;
default:
printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
break;
}
}
static uint32_t pxa2xx_cp14_read(void *opaque, int op2, int reg, int crm)
{
switch (crm) {
case 0:
return pxa2xx_clkpwr_read(opaque, op2, reg, crm);
default:
printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
break;
}
return 0; return 0;
} }
static void pxa2xx_cp14_write(void *opaque, int op2, int reg, int crm,
uint32_t value)
{
switch (crm) {
case 0:
pxa2xx_clkpwr_write(opaque, op2, reg, crm, value);
break;
default:
printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
break;
}
}
static int pxa2xx_cppmnc_read(CPUARMState *env, const ARMCPRegInfo *ri, static int pxa2xx_cppmnc_read(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t *value) uint64_t *value)
{ {
@ -400,6 +365,14 @@ static const ARMCPRegInfo pxa_cp_reginfo[] = {
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
{ .name = "CPPMN3", .cp = 14, .crn = 2, .crm = 3, .opc1 = 0, .opc2 = 0, { .name = "CPPMN3", .cp = 14, .crn = 2, .crm = 3, .opc1 = 0, .opc2 = 0,
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
/* cp14 crn==6: CLKCFG */
{ .name = "CLKCFG", .cp = 14, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
.access = PL1_RW,
.readfn = pxa2xx_clkcfg_read, .writefn = pxa2xx_clkcfg_write },
/* cp14 crn==7: PWRMODE */
{ .name = "PWRMODE", .cp = 14, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 0,
.access = PL1_RW,
.readfn = arm_cp_read_zero, .writefn = pxa2xx_pwrmode_write },
REGINFO_SENTINEL REGINFO_SENTINEL
}; };
@ -2111,7 +2084,6 @@ PXA2xxState *pxa270_init(MemoryRegion *address_space,
memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem); memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem);
vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s); vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s);
cpu_arm_set_cp_io(&s->cpu->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);
pxa2xx_setup_cp14(s); pxa2xx_setup_cp14(s);
s->mm_base = 0x48000000; s->mm_base = 0x48000000;
@ -2243,7 +2215,6 @@ PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size)
memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem); memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem);
vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s); vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s);
cpu_arm_set_cp_io(&s->cpu->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);
pxa2xx_setup_cp14(s); pxa2xx_setup_cp14(s);
s->mm_base = 0x48000000; s->mm_base = 0x48000000;