mirror of https://github.com/proxmox/mirror_qemu
target-mips: Add ASE DSP branch instructions
Add MIPS ASE DSP Branch instructions. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>master
parent
4133498f8e
commit
e45a93e259
|
@ -332,6 +332,14 @@ enum {
|
||||||
OPC_DSHD = (0x05 << 6) | OPC_DBSHFL,
|
OPC_DSHD = (0x05 << 6) | OPC_DBSHFL,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
/* MIPS DSP REGIMM opcodes */
|
||||||
|
enum {
|
||||||
|
OPC_BPOSGE32 = (0x1C << 16) | OPC_REGIMM,
|
||||||
|
#if defined(TARGET_MIPS64)
|
||||||
|
OPC_BPOSGE64 = (0x1D << 16) | OPC_REGIMM,
|
||||||
|
#endif
|
||||||
|
};
|
||||||
|
|
||||||
/* Coprocessor 0 (rs field) */
|
/* Coprocessor 0 (rs field) */
|
||||||
#define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
|
#define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
|
||||||
|
|
||||||
|
@ -3230,6 +3238,16 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
|
||||||
}
|
}
|
||||||
btgt = ctx->pc + insn_bytes + offset;
|
btgt = ctx->pc + insn_bytes + offset;
|
||||||
break;
|
break;
|
||||||
|
case OPC_BPOSGE32:
|
||||||
|
#if defined(TARGET_MIPS64)
|
||||||
|
case OPC_BPOSGE64:
|
||||||
|
tcg_gen_andi_tl(t0, cpu_dspctrl, 0x7F);
|
||||||
|
#else
|
||||||
|
tcg_gen_andi_tl(t0, cpu_dspctrl, 0x3F);
|
||||||
|
#endif
|
||||||
|
bcond_compute = 1;
|
||||||
|
btgt = ctx->pc + insn_bytes + offset;
|
||||||
|
break;
|
||||||
case OPC_J:
|
case OPC_J:
|
||||||
case OPC_JAL:
|
case OPC_JAL:
|
||||||
case OPC_JALX:
|
case OPC_JALX:
|
||||||
|
@ -3418,6 +3436,16 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
|
||||||
tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0);
|
tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0);
|
||||||
MIPS_DEBUG("bltzl %s, " TARGET_FMT_lx, regnames[rs], btgt);
|
MIPS_DEBUG("bltzl %s, " TARGET_FMT_lx, regnames[rs], btgt);
|
||||||
goto likely;
|
goto likely;
|
||||||
|
case OPC_BPOSGE32:
|
||||||
|
tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 32);
|
||||||
|
MIPS_DEBUG("bposge32 " TARGET_FMT_lx, btgt);
|
||||||
|
goto not_likely;
|
||||||
|
#if defined(TARGET_MIPS64)
|
||||||
|
case OPC_BPOSGE64:
|
||||||
|
tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 64);
|
||||||
|
MIPS_DEBUG("bposge64 " TARGET_FMT_lx, btgt);
|
||||||
|
goto not_likely;
|
||||||
|
#endif
|
||||||
case OPC_BLTZALS:
|
case OPC_BLTZALS:
|
||||||
case OPC_BLTZAL:
|
case OPC_BLTZAL:
|
||||||
ctx->hflags |= (opc == OPC_BLTZALS
|
ctx->hflags |= (opc == OPC_BLTZALS
|
||||||
|
@ -12589,6 +12617,14 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch)
|
||||||
check_insn(env, ctx, ISA_MIPS32R2);
|
check_insn(env, ctx, ISA_MIPS32R2);
|
||||||
/* Treat as NOP. */
|
/* Treat as NOP. */
|
||||||
break;
|
break;
|
||||||
|
case OPC_BPOSGE32: /* MIPS DSP branch */
|
||||||
|
#if defined(TARGET_MIPS64)
|
||||||
|
case OPC_BPOSGE64:
|
||||||
|
#endif
|
||||||
|
check_dsp(ctx);
|
||||||
|
gen_compute_branch(ctx, op1, 4, -1, -2, (int32_t)imm << 2);
|
||||||
|
*is_branch = 1;
|
||||||
|
break;
|
||||||
default: /* Invalid */
|
default: /* Invalid */
|
||||||
MIPS_INVAL("regimm");
|
MIPS_INVAL("regimm");
|
||||||
generate_exception(ctx, EXCP_RI);
|
generate_exception(ctx, EXCP_RI);
|
||||||
|
|
Loading…
Reference in New Issue