mirror of https://github.com/proxmox/mirror_qemu
ich9: Add acpi support and definitions
Lay the groundwork for subsequent ich9 support. Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp> Signed-off-by: Jason Baron <jbaron@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>master
Jason Baron
Anthony Liguori
parent
410edd922d
commit
e516572fde
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@ -28,7 +28,7 @@ common-obj-$(CONFIG_I8254) += i8254_common.o i8254.o
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common-obj-$(CONFIG_PCSPK) += pcspk.o
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common-obj-$(CONFIG_PCKBD) += pckbd.o
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common-obj-$(CONFIG_FDC) += fdc.o
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common-obj-$(CONFIG_ACPI) += acpi.o acpi_piix4.o
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common-obj-$(CONFIG_ACPI) += acpi.o acpi_piix4.o acpi_ich9.o
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common-obj-$(CONFIG_APM) += pm_smbus.o apm.o
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common-obj-$(CONFIG_DMA) += dma.o
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common-obj-$(CONFIG_I82374) += i82374.o
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@ -0,0 +1,315 @@
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/*
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* ACPI implementation
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*
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* Copyright (c) 2006 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License version 2 as published by the Free Software Foundation.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>
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*/
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/*
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* Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
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* VA Linux Systems Japan K.K.
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* Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
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*
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* This is based on acpi.c.
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*/
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#include "hw.h"
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#include "pc.h"
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#include "pci.h"
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#include "qemu-timer.h"
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#include "sysemu.h"
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#include "acpi.h"
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#include "ich9.h"
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//#define DEBUG
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#ifdef DEBUG
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#define ICH9_DEBUG(fmt, ...) \
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do { printf("%s "fmt, __func__, ## __VA_ARGS__); } while (0)
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#else
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#define ICH9_DEBUG(fmt, ...) do { } while (0)
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#endif
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static void pm_ioport_write_fallback(void *opaque, uint32_t addr, int len,
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uint32_t val);
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static uint32_t pm_ioport_read_fallback(void *opaque, uint32_t addr, int len);
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static void pm_update_sci(ICH9LPCPMRegs *pm)
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{
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int sci_level, pm1a_sts;
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pm1a_sts = acpi_pm1_evt_get_sts(&pm->acpi_regs);
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sci_level = (((pm1a_sts & pm->acpi_regs.pm1.evt.en) &
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(ACPI_BITMASK_RT_CLOCK_ENABLE |
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ACPI_BITMASK_POWER_BUTTON_ENABLE |
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ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
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ACPI_BITMASK_TIMER_ENABLE)) != 0);
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qemu_set_irq(pm->irq, sci_level);
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/* schedule a timer interruption if needed */
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acpi_pm_tmr_update(&pm->acpi_regs,
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(pm->acpi_regs.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) &&
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!(pm1a_sts & ACPI_BITMASK_TIMER_STATUS));
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}
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static void ich9_pm_update_sci_fn(ACPIREGS *regs)
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{
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ICH9LPCPMRegs *pm = container_of(regs, ICH9LPCPMRegs, acpi_regs);
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pm_update_sci(pm);
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}
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static void pm_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
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{
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ICH9LPCPMRegs *pm = opaque;
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switch (addr & ICH9_PMIO_MASK) {
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case ICH9_PMIO_GPE0_STS ... (ICH9_PMIO_GPE0_STS + ICH9_PMIO_GPE0_LEN - 1):
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acpi_gpe_ioport_writeb(&pm->acpi_regs, addr, val);
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break;
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default:
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break;
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}
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ICH9_DEBUG("port=0x%04x val=0x%04x\n", addr, val);
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}
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static uint32_t pm_ioport_readb(void *opaque, uint32_t addr)
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{
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ICH9LPCPMRegs *pm = opaque;
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uint32_t val = 0;
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switch (addr & ICH9_PMIO_MASK) {
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case ICH9_PMIO_GPE0_STS ... (ICH9_PMIO_GPE0_STS + ICH9_PMIO_GPE0_LEN - 1):
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val = acpi_gpe_ioport_readb(&pm->acpi_regs, addr);
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break;
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default:
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val = 0;
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break;
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}
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ICH9_DEBUG("port=0x%04x val=0x%04x\n", addr, val);
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return val;
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}
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static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
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{
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ICH9LPCPMRegs *pm = opaque;
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switch (addr & ICH9_PMIO_MASK) {
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case ICH9_PMIO_PM1_STS:
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acpi_pm1_evt_write_sts(&pm->acpi_regs, val);
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pm_update_sci(pm);
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break;
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case ICH9_PMIO_PM1_EN:
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pm->acpi_regs.pm1.evt.en = val;
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pm_update_sci(pm);
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break;
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case ICH9_PMIO_PM1_CNT:
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acpi_pm1_cnt_write(&pm->acpi_regs, val, 0);
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break;
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default:
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pm_ioport_write_fallback(opaque, addr, 2, val);
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break;
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}
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ICH9_DEBUG("port=0x%04x val=0x%04x\n", addr, val);
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}
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static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
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{
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ICH9LPCPMRegs *pm = opaque;
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uint32_t val;
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switch (addr & ICH9_PMIO_MASK) {
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case ICH9_PMIO_PM1_STS:
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val = acpi_pm1_evt_get_sts(&pm->acpi_regs);
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break;
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case ICH9_PMIO_PM1_EN:
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val = pm->acpi_regs.pm1.evt.en;
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break;
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case ICH9_PMIO_PM1_CNT:
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val = pm->acpi_regs.pm1.cnt.cnt;
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break;
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default:
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val = pm_ioport_read_fallback(opaque, addr, 2);
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break;
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}
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ICH9_DEBUG("port=0x%04x val=0x%04x\n", addr, val);
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return val;
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}
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static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
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{
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ICH9LPCPMRegs *pm = opaque;
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switch (addr & ICH9_PMIO_MASK) {
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case ICH9_PMIO_SMI_EN:
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pm->smi_en = val;
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break;
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default:
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pm_ioport_write_fallback(opaque, addr, 4, val);
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break;
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}
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ICH9_DEBUG("port=0x%04x val=0x%08x\n", addr, val);
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}
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static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
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{
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ICH9LPCPMRegs *pm = opaque;
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uint32_t val;
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switch (addr & ICH9_PMIO_MASK) {
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case ICH9_PMIO_PM1_TMR:
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val = acpi_pm_tmr_get(&pm->acpi_regs);
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break;
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case ICH9_PMIO_SMI_EN:
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val = pm->smi_en;
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break;
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default:
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val = pm_ioport_read_fallback(opaque, addr, 4);
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break;
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}
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ICH9_DEBUG("port=0x%04x val=0x%08x\n", addr, val);
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return val;
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}
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static void pm_ioport_write_fallback(void *opaque, uint32_t addr, int len,
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uint32_t val)
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{
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int subsize = (len == 4) ? 2 : 1;
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IOPortWriteFunc *ioport_write =
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(subsize == 2) ? pm_ioport_writew : pm_ioport_writeb;
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int i;
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for (i = 0; i < len; i += subsize) {
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ioport_write(opaque, addr, val);
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val >>= 8 * subsize;
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}
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}
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static uint32_t pm_ioport_read_fallback(void *opaque, uint32_t addr, int len)
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{
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int subsize = (len == 4) ? 2 : 1;
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IOPortReadFunc *ioport_read =
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(subsize == 2) ? pm_ioport_readw : pm_ioport_readb;
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uint32_t val;
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int i;
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val = 0;
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for (i = 0; i < len; i += subsize) {
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val <<= 8 * subsize;
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val |= ioport_read(opaque, addr);
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}
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return val;
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}
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void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base)
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{
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ICH9_DEBUG("to 0x%x\n", pm_io_base);
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assert((pm_io_base & ICH9_PMIO_MASK) == 0);
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if (pm->pm_io_base != 0) {
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isa_unassign_ioport(pm->pm_io_base, ICH9_PMIO_SIZE);
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}
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/* don't map at 0 */
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if (pm_io_base == 0) {
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return;
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}
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register_ioport_write(pm_io_base, ICH9_PMIO_SIZE, 1, pm_ioport_writeb, pm);
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register_ioport_read(pm_io_base, ICH9_PMIO_SIZE, 1, pm_ioport_readb, pm);
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register_ioport_write(pm_io_base, ICH9_PMIO_SIZE, 2, pm_ioport_writew, pm);
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register_ioport_read(pm_io_base, ICH9_PMIO_SIZE, 2, pm_ioport_readw, pm);
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register_ioport_write(pm_io_base, ICH9_PMIO_SIZE, 4, pm_ioport_writel, pm);
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register_ioport_read(pm_io_base, ICH9_PMIO_SIZE, 4, pm_ioport_readl, pm);
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pm->pm_io_base = pm_io_base;
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acpi_gpe_blk(&pm->acpi_regs, pm_io_base + ICH9_PMIO_GPE0_STS);
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}
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static int ich9_pm_post_load(void *opaque, int version_id)
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{
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ICH9LPCPMRegs *pm = opaque;
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uint32_t pm_io_base = pm->pm_io_base;
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pm->pm_io_base = 0;
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ich9_pm_iospace_update(pm, pm_io_base);
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return 0;
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}
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#define VMSTATE_GPE_ARRAY(_field, _state) \
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{ \
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.name = (stringify(_field)), \
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.version_id = 0, \
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.num = ICH9_PMIO_GPE0_LEN, \
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.info = &vmstate_info_uint8, \
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.size = sizeof(uint8_t), \
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.flags = VMS_ARRAY | VMS_POINTER, \
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.offset = vmstate_offset_pointer(_state, _field, uint8_t), \
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}
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const VMStateDescription vmstate_ich9_pm = {
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.name = "ich9_pm",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.post_load = ich9_pm_post_load,
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.fields = (VMStateField[]) {
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VMSTATE_UINT16(acpi_regs.pm1.evt.sts, ICH9LPCPMRegs),
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VMSTATE_UINT16(acpi_regs.pm1.evt.en, ICH9LPCPMRegs),
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VMSTATE_UINT16(acpi_regs.pm1.cnt.cnt, ICH9LPCPMRegs),
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VMSTATE_TIMER(acpi_regs.tmr.timer, ICH9LPCPMRegs),
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VMSTATE_INT64(acpi_regs.tmr.overflow_time, ICH9LPCPMRegs),
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VMSTATE_GPE_ARRAY(acpi_regs.gpe.sts, ICH9LPCPMRegs),
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VMSTATE_GPE_ARRAY(acpi_regs.gpe.en, ICH9LPCPMRegs),
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VMSTATE_UINT32(smi_en, ICH9LPCPMRegs),
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VMSTATE_UINT32(smi_sts, ICH9LPCPMRegs),
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VMSTATE_END_OF_LIST()
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}
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};
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static void pm_reset(void *opaque)
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{
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ICH9LPCPMRegs *pm = opaque;
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ich9_pm_iospace_update(pm, 0);
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acpi_pm1_evt_reset(&pm->acpi_regs);
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acpi_pm1_cnt_reset(&pm->acpi_regs);
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acpi_pm_tmr_reset(&pm->acpi_regs);
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acpi_gpe_reset(&pm->acpi_regs);
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pm_update_sci(pm);
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}
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static void pm_powerdown_req(Notifier *n, void *opaque)
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{
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ICH9LPCPMRegs *pm = container_of(n, ICH9LPCPMRegs, powerdown_notifier);
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acpi_pm1_evt_power_down(&pm->acpi_regs);
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}
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void ich9_pm_init(ICH9LPCPMRegs *pm, qemu_irq sci_irq, qemu_irq cmos_s3)
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{
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acpi_pm_tmr_init(&pm->acpi_regs, ich9_pm_update_sci_fn);
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acpi_pm1_cnt_init(&pm->acpi_regs);
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acpi_gpe_init(&pm->acpi_regs, ICH9_PMIO_GPE0_LEN);
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pm->irq = sci_irq;
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qemu_register_reset(pm_reset, pm);
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pm->powerdown_notifier.notify = pm_powerdown_req;
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qemu_register_powerdown_notifier(&pm->powerdown_notifier);
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}
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@ -0,0 +1,47 @@
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/*
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* QEMU GMCH/ICH9 LPC PM Emulation
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*
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* Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
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* VA Linux Systems Japan K.K.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>
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*/
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#ifndef HW_ACPI_ICH9_H
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#define HW_ACPI_ICH9_H
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#include "acpi.h"
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typedef struct ICH9LPCPMRegs {
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/*
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* In ich9 spec says that pm1_cnt register is 32bit width and
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* that the upper 16bits are reserved and unused.
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* PM1a_CNT_BLK = 2 in FADT so it is defined as uint16_t.
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*/
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ACPIREGS acpi_regs;
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uint32_t smi_en;
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uint32_t smi_sts;
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qemu_irq irq; /* SCI */
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uint32_t pm_io_base;
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Notifier powerdown_notifier;
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} ICH9LPCPMRegs;
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void ich9_pm_init(ICH9LPCPMRegs *pm,
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qemu_irq sci_irq, qemu_irq cmos_s3_resume);
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void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base);
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extern const VMStateDescription vmstate_ich9_pm;
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#endif /* HW_ACPI_ICH9_H */
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@ -0,0 +1,207 @@
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#ifndef HW_ICH9_H
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#define HW_ICH9_H
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#include "hw.h"
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#include "range.h"
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#include "isa.h"
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#include "sysbus.h"
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#include "pc.h"
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#include "apm.h"
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#include "ioapic.h"
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#include "pci.h"
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#include "pcie_host.h"
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#include "pci_bridge.h"
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#include "acpi.h"
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#include "acpi_ich9.h"
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#include "pam.h"
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#include "pci_internals.h"
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void ich9_lpc_set_irq(void *opaque, int irq_num, int level);
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int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx);
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void ich9_lpc_pm_init(PCIDevice *pci_lpc, qemu_irq cmos_s3);
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PCIBus *ich9_d2pbr_init(PCIBus *bus, int devfn, int sec_bus);
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i2c_bus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
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#define ICH9_CC_SIZE (16 * 1024) /* 16KB */
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#define TYPE_ICH9_LPC_DEVICE "ICH9 LPC"
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#define ICH9_LPC_DEVICE(obj) \
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OBJECT_CHECK(ICH9LPCState, (obj), TYPE_ICH9_LPC_DEVICE)
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typedef struct ICH9LPCState {
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/* ICH9 LPC PCI to ISA bridge */
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PCIDevice d;
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/* (pci device, intx) -> pirq
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* In real chipset case, the unused slots are never used
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* as ICH9 supports only D25-D32 irq routing.
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* On the other hand in qemu case, any slot/function can be populated
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* via command line option.
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* So fallback interrupt routing for any devices in any slots is necessary.
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*/
|
||||
uint8_t irr[PCI_SLOT_MAX][PCI_NUM_PINS];
|
||||
|
||||
APMState apm;
|
||||
ICH9LPCPMRegs pm;
|
||||
uint32_t sci_level; /* track sci level */
|
||||
|
||||
/* 10.1 Chipset Configuration registers(Memory Space)
|
||||
which is pointed by RCBA */
|
||||
uint8_t chip_config[ICH9_CC_SIZE];
|
||||
/* isa bus */
|
||||
ISABus *isa_bus;
|
||||
MemoryRegion rbca_mem;
|
||||
|
||||
qemu_irq *pic;
|
||||
qemu_irq *ioapic;
|
||||
} ICH9LPCState;
|
||||
|
||||
#define Q35_MASK(bit, ms_bit, ls_bit) \
|
||||
((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1)))
|
||||
|
||||
/* ICH9: Chipset Configuration Registers */
|
||||
#define ICH9_CC_ADDR_MASK (ICH9_CC_SIZE - 1)
|
||||
|
||||
#define ICH9_CC
|
||||
#define ICH9_CC_D28IP 0x310C
|
||||
#define ICH9_CC_D28IP_SHIFT 4
|
||||
#define ICH9_CC_D28IP_MASK 0xf
|
||||
#define ICH9_CC_D28IP_DEFAULT 0x00214321
|
||||
#define ICH9_CC_D31IR 0x3140
|
||||
#define ICH9_CC_D30IR 0x3142
|
||||
#define ICH9_CC_D29IR 0x3144
|
||||
#define ICH9_CC_D28IR 0x3146
|
||||
#define ICH9_CC_D27IR 0x3148
|
||||
#define ICH9_CC_D26IR 0x314C
|
||||
#define ICH9_CC_D25IR 0x3150
|
||||
#define ICH9_CC_DIR_DEFAULT 0x3210
|
||||
#define ICH9_CC_D30IR_DEFAULT 0x0
|
||||
#define ICH9_CC_DIR_SHIFT 4
|
||||
#define ICH9_CC_DIR_MASK 0x7
|
||||
#define ICH9_CC_OIC 0x31FF
|
||||
#define ICH9_CC_OIC_AEN 0x1
|
||||
|
||||
/* D28:F[0-5] */
|
||||
#define ICH9_PCIE_DEV 28
|
||||
#define ICH9_PCIE_FUNC_MAX 6
|
||||
|
||||
|
||||
/* D29:F0 USB UHCI Controller #1 */
|
||||
#define ICH9_USB_UHCI1_DEV 29
|
||||
#define ICH9_USB_UHCI1_FUNC 0
|
||||
|
||||
/* D30:F0 DMI-to-PCI brdige */
|
||||
#define ICH9_D2P_BRIDGE "ICH9 D2P BRIDGE"
|
||||
#define ICH9_D2P_BRIDGE_SAVEVM_VERSION 0
|
||||
|
||||
#define ICH9_D2P_BRIDGE_DEV 30
|
||||
#define ICH9_D2P_BRIDGE_FUNC 0
|
||||
|
||||
#define ICH9_D2P_SECONDARY_DEFAULT (256 - 8)
|
||||
|
||||
#define ICH9_D2P_A2_REVISION 0x92
|
||||
|
||||
|
||||
/* D31:F1 LPC controller */
|
||||
#define ICH9_A2_LPC "ICH9 A2 LPC"
|
||||
#define ICH9_A2_LPC_SAVEVM_VERSION 0
|
||||
|
||||
#define ICH9_LPC_DEV 31
|
||||
#define ICH9_LPC_FUNC 0
|
||||
|
||||
#define ICH9_A2_LPC_REVISION 0x2
|
||||
#define ICH9_LPC_NB_PIRQS 8 /* PCI A-H */
|
||||
|
||||
#define ICH9_LPC_PMBASE 0x40
|
||||
#define ICH9_LPC_PMBASE_BASE_ADDRESS_MASK Q35_MASK(32, 15, 7)
|
||||
#define ICH9_LPC_PMBASE_RTE 0x1
|
||||
#define ICH9_LPC_PMBASE_DEFAULT 0x1
|
||||
#define ICH9_LPC_ACPI_CTRL 0x44
|
||||
#define ICH9_LPC_ACPI_CTRL_ACPI_EN 0x80
|
||||
#define ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK Q35_MASK(8, 2, 0)
|
||||
#define ICH9_LPC_ACPI_CTRL_9 0x0
|
||||
#define ICH9_LPC_ACPI_CTRL_10 0x1
|
||||
#define ICH9_LPC_ACPI_CTRL_11 0x2
|
||||
#define ICH9_LPC_ACPI_CTRL_20 0x4
|
||||
#define ICH9_LPC_ACPI_CTRL_21 0x5
|
||||
#define ICH9_LPC_ACPI_CTRL_DEFAULT 0x0
|
||||
|
||||
#define ICH9_LPC_PIRQA_ROUT 0x60
|
||||
#define ICH9_LPC_PIRQB_ROUT 0x61
|
||||
#define ICH9_LPC_PIRQC_ROUT 0x62
|
||||
#define ICH9_LPC_PIRQD_ROUT 0x63
|
||||
|
||||
#define ICH9_LPC_PIRQE_ROUT 0x68
|
||||
#define ICH9_LPC_PIRQF_ROUT 0x69
|
||||
#define ICH9_LPC_PIRQG_ROUT 0x6a
|
||||
#define ICH9_LPC_PIRQH_ROUT 0x6b
|
||||
|
||||
#define ICH9_LPC_PIRQ_ROUT_IRQEN 0x80
|
||||
#define ICH9_LPC_PIRQ_ROUT_MASK Q35_MASK(8, 3, 0)
|
||||
#define ICH9_LPC_PIRQ_ROUT_DEFAULT 0x80
|
||||
|
||||
#define ICH9_LPC_RCBA 0xf0
|
||||
#define ICH9_LPC_RCBA_BA_MASK Q35_MASK(32, 31, 14)
|
||||
#define ICH9_LPC_RCBA_EN 0x1
|
||||
#define ICH9_LPC_RCBA_DEFAULT 0x0
|
||||
|
||||
#define ICH9_LPC_PIC_NUM_PINS 16
|
||||
#define ICH9_LPC_IOAPIC_NUM_PINS 24
|
||||
|
||||
/* D31:F2 SATA Controller #1 */
|
||||
#define ICH9_SATA1_DEV 31
|
||||
#define ICH9_SATA1_FUNC 2
|
||||
|
||||
/* D30:F1 power management I/O registers
|
||||
offset from the address ICH9_LPC_PMBASE */
|
||||
|
||||
/* ICH9 LPC PM I/O registers are 128 ports and 128-aligned */
|
||||
#define ICH9_PMIO_SIZE 128
|
||||
#define ICH9_PMIO_MASK (ICH9_PMIO_SIZE - 1)
|
||||
|
||||
#define ICH9_PMIO_PM1_STS 0x00
|
||||
#define ICH9_PMIO_PM1_EN 0x02
|
||||
#define ICH9_PMIO_PM1_CNT 0x04
|
||||
#define ICH9_PMIO_PM1_TMR 0x08
|
||||
#define ICH9_PMIO_GPE0_STS 0x20
|
||||
#define ICH9_PMIO_GPE0_EN 0x28
|
||||
#define ICH9_PMIO_GPE0_LEN 16
|
||||
#define ICH9_PMIO_SMI_EN 0x30
|
||||
#define ICH9_PMIO_SMI_EN_APMC_EN (1 << 5)
|
||||
#define ICH9_PMIO_SMI_STS 0x34
|
||||
|
||||
/* FADT ACPI_ENABLE/ACPI_DISABLE */
|
||||
#define ICH9_APM_ACPI_ENABLE 0x2
|
||||
#define ICH9_APM_ACPI_DISABLE 0x3
|
||||
|
||||
|
||||
/* D31:F3 SMBus controller */
|
||||
#define ICH9_A2_SMB_REVISION 0x02
|
||||
#define ICH9_SMB_PI 0x00
|
||||
|
||||
#define ICH9_SMB_SMBMBAR0 0x10
|
||||
#define ICH9_SMB_SMBMBAR1 0x14
|
||||
#define ICH9_SMB_SMBM_BAR 0
|
||||
#define ICH9_SMB_SMBM_SIZE (1 << 8)
|
||||
#define ICH9_SMB_SMB_BASE 0x20
|
||||
#define ICH9_SMB_SMB_BASE_BAR 4
|
||||
#define ICH9_SMB_SMB_BASE_SIZE (1 << 5)
|
||||
#define ICH9_SMB_HOSTC 0x40
|
||||
#define ICH9_SMB_HOSTC_SSRESET ((uint8_t)(1 << 3))
|
||||
#define ICH9_SMB_HOSTC_I2C_EN ((uint8_t)(1 << 2))
|
||||
#define ICH9_SMB_HOSTC_SMB_SMI_EN ((uint8_t)(1 << 1))
|
||||
#define ICH9_SMB_HOSTC_HST_EN ((uint8_t)(1 << 0))
|
||||
|
||||
/* D31:F3 SMBus I/O and memory mapped I/O registers */
|
||||
#define ICH9_SMB_DEV 31
|
||||
#define ICH9_SMB_FUNC 3
|
||||
|
||||
#define ICH9_SMB_HST_STS 0x00
|
||||
#define ICH9_SMB_HST_CNT 0x02
|
||||
#define ICH9_SMB_HST_CMD 0x03
|
||||
#define ICH9_SMB_XMIT_SLVA 0x04
|
||||
#define ICH9_SMB_HST_D0 0x05
|
||||
#define ICH9_SMB_HST_D1 0x06
|
||||
#define ICH9_SMB_HOST_BLOCK_DB 0x07
|
||||
|
||||
#endif /* HW_ICH9_H */
|
||||
12
hw/pci_ids.h
12
hw/pci_ids.h
|
|
@ -36,6 +36,7 @@
|
|||
#define PCI_CLASS_BRIDGE_HOST 0x0600
|
||||
#define PCI_CLASS_BRIDGE_ISA 0x0601
|
||||
#define PCI_CLASS_BRIDGE_PCI 0x0604
|
||||
#define PCI_CLASS_BRDIGE_PCI_INF_SUB 0x01
|
||||
#define PCI_CLASS_BRIDGE_OTHER 0x0680
|
||||
|
||||
#define PCI_CLASS_COMMUNICATION_SERIAL 0x0700
|
||||
|
|
@ -116,6 +117,17 @@
|
|||
#define PCI_DEVICE_ID_INTEL_82371AB 0x7111
|
||||
#define PCI_DEVICE_ID_INTEL_82371AB_2 0x7112
|
||||
#define PCI_DEVICE_ID_INTEL_82371AB_3 0x7113
|
||||
|
||||
#define PCI_DEVICE_ID_INTEL_ICH9_0 0x2910
|
||||
#define PCI_DEVICE_ID_INTEL_ICH9_1 0x2917
|
||||
#define PCI_DEVICE_ID_INTEL_ICH9_2 0x2912
|
||||
#define PCI_DEVICE_ID_INTEL_ICH9_3 0x2913
|
||||
#define PCI_DEVICE_ID_INTEL_ICH9_4 0x2914
|
||||
#define PCI_DEVICE_ID_INTEL_ICH9_5 0x2919
|
||||
#define PCI_DEVICE_ID_INTEL_ICH9_6 0x2930
|
||||
#define PCI_DEVICE_ID_INTEL_ICH9_7 0x2916
|
||||
#define PCI_DEVICE_ID_INTEL_ICH9_8 0x2918
|
||||
|
||||
#define PCI_DEVICE_ID_INTEL_82801I_UHCI1 0x2934
|
||||
#define PCI_DEVICE_ID_INTEL_82801I_UHCI2 0x2935
|
||||
#define PCI_DEVICE_ID_INTEL_82801I_UHCI3 0x2936
|
||||
|
|
|
|||
Loading…
Reference in New Issue