mirror of https://github.com/proxmox/mirror_qemu
ppc: rename gen_set_cr6_from_fpscr
It sets CR1, not CR6 (and the spec agrees). Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Tom Musta <tommusta@gmail.com> Tested-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>master
parent
ebbd8b40a9
commit
e57d02022c
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@ -8221,7 +8221,7 @@ static inline TCGv_ptr gen_fprp_ptr(int reg)
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}
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}
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#if defined(TARGET_PPC64)
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#if defined(TARGET_PPC64)
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static void gen_set_cr6_from_fpscr(DisasContext *ctx)
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static void gen_set_cr1_from_fpscr(DisasContext *ctx)
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{
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{
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TCGv_i32 tmp = tcg_temp_new_i32();
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TCGv_i32 tmp = tcg_temp_new_i32();
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tcg_gen_trunc_tl_i32(tmp, cpu_fpscr);
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tcg_gen_trunc_tl_i32(tmp, cpu_fpscr);
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@ -8229,7 +8229,7 @@ static void gen_set_cr6_from_fpscr(DisasContext *ctx)
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tcg_temp_free_i32(tmp);
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tcg_temp_free_i32(tmp);
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}
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}
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#else
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#else
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static void gen_set_cr6_from_fpscr(DisasContext *ctx)
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static void gen_set_cr1_from_fpscr(DisasContext *ctx)
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{
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{
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tcg_gen_shri_tl(cpu_crf[1], cpu_fpscr, 28);
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tcg_gen_shri_tl(cpu_crf[1], cpu_fpscr, 28);
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}
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}
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@ -8249,7 +8249,7 @@ static void gen_##name(DisasContext *ctx) \
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rb = gen_fprp_ptr(rB(ctx->opcode)); \
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rb = gen_fprp_ptr(rB(ctx->opcode)); \
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gen_helper_##name(cpu_env, rd, ra, rb); \
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gen_helper_##name(cpu_env, rd, ra, rb); \
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if (unlikely(Rc(ctx->opcode) != 0)) { \
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if (unlikely(Rc(ctx->opcode) != 0)) { \
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gen_set_cr6_from_fpscr(ctx); \
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gen_set_cr1_from_fpscr(ctx); \
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} \
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} \
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tcg_temp_free_ptr(rd); \
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tcg_temp_free_ptr(rd); \
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tcg_temp_free_ptr(ra); \
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tcg_temp_free_ptr(ra); \
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@ -8307,7 +8307,7 @@ static void gen_##name(DisasContext *ctx) \
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u32_2 = tcg_const_i32(u32f2(ctx->opcode)); \
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u32_2 = tcg_const_i32(u32f2(ctx->opcode)); \
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gen_helper_##name(cpu_env, rt, rb, u32_1, u32_2); \
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gen_helper_##name(cpu_env, rt, rb, u32_1, u32_2); \
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if (unlikely(Rc(ctx->opcode) != 0)) { \
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if (unlikely(Rc(ctx->opcode) != 0)) { \
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gen_set_cr6_from_fpscr(ctx); \
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gen_set_cr1_from_fpscr(ctx); \
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} \
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} \
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tcg_temp_free_ptr(rt); \
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tcg_temp_free_ptr(rt); \
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tcg_temp_free_ptr(rb); \
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tcg_temp_free_ptr(rb); \
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@ -8331,7 +8331,7 @@ static void gen_##name(DisasContext *ctx) \
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i32 = tcg_const_i32(i32fld(ctx->opcode)); \
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i32 = tcg_const_i32(i32fld(ctx->opcode)); \
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gen_helper_##name(cpu_env, rt, ra, rb, i32); \
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gen_helper_##name(cpu_env, rt, ra, rb, i32); \
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if (unlikely(Rc(ctx->opcode) != 0)) { \
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if (unlikely(Rc(ctx->opcode) != 0)) { \
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gen_set_cr6_from_fpscr(ctx); \
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gen_set_cr1_from_fpscr(ctx); \
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} \
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} \
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tcg_temp_free_ptr(rt); \
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tcg_temp_free_ptr(rt); \
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tcg_temp_free_ptr(rb); \
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tcg_temp_free_ptr(rb); \
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@ -8352,7 +8352,7 @@ static void gen_##name(DisasContext *ctx) \
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rb = gen_fprp_ptr(rB(ctx->opcode)); \
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rb = gen_fprp_ptr(rB(ctx->opcode)); \
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gen_helper_##name(cpu_env, rt, rb); \
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gen_helper_##name(cpu_env, rt, rb); \
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if (unlikely(Rc(ctx->opcode) != 0)) { \
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if (unlikely(Rc(ctx->opcode) != 0)) { \
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gen_set_cr6_from_fpscr(ctx); \
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gen_set_cr1_from_fpscr(ctx); \
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} \
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} \
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tcg_temp_free_ptr(rt); \
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tcg_temp_free_ptr(rt); \
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tcg_temp_free_ptr(rb); \
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tcg_temp_free_ptr(rb); \
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@ -8373,7 +8373,7 @@ static void gen_##name(DisasContext *ctx) \
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i32 = tcg_const_i32(i32fld(ctx->opcode)); \
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i32 = tcg_const_i32(i32fld(ctx->opcode)); \
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gen_helper_##name(cpu_env, rt, rs, i32); \
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gen_helper_##name(cpu_env, rt, rs, i32); \
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if (unlikely(Rc(ctx->opcode) != 0)) { \
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if (unlikely(Rc(ctx->opcode) != 0)) { \
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gen_set_cr6_from_fpscr(ctx); \
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gen_set_cr1_from_fpscr(ctx); \
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} \
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} \
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tcg_temp_free_ptr(rt); \
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tcg_temp_free_ptr(rt); \
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tcg_temp_free_ptr(rs); \
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tcg_temp_free_ptr(rs); \
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