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sparc64: mmu bypass mode correction 

This Implement physical address truncation in mmu bypass mode.
IMMU bypass is also active when cpu enters RED_STATE

Signed-off-by: igor.v.kovalenko@gmail.com

--
Kind regards,
Igor V. Kovalenko
master
Igor Kovalenko 2009-07-12 07:41:42 +00:00 committed by Blue Swirl
parent 616cbc78a5
commit e8807b14cc
1 changed files with 11 additions and 3 deletions
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14
target-sparc/helper.c
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@ -369,6 +369,13 @@ void dump_mmu(CPUState *env)
#endif /* DEBUG_MMU */
#else /* !TARGET_SPARC64 */
// 41 bit physical address space
static inline target_phys_addr_t ultrasparc_truncate_physical(uint64_t x)
{
return x & 0x1ffffffffffULL;
}
/*
* UltraSparc IIi I/DMMUs
*/
@ -380,7 +387,7 @@ static int get_physical_address_data(CPUState *env,
unsigned int i;
if ((env->lsu & DMMU_E) == 0) { /* DMMU disabled */
*physical = address;
*physical = ultrasparc_truncate_physical(address);
*prot = PAGE_READ | PAGE_WRITE;
return 0;
}
@ -442,8 +449,9 @@ static int get_physical_address_code(CPUState *env,
target_ulong mask;
unsigned int i;
if ((env->lsu & IMMU_E) == 0) { /* IMMU disabled */
*physical = address;
if ((env->lsu & IMMU_E) == 0 || (env->pstate & PS_RED) != 0) {
/* IMMU disabled */
*physical = ultrasparc_truncate_physical(address);
*prot = PAGE_EXEC;
return 0;
}