mirror of https://github.com/proxmox/mirror_qemu
tests/tcg/xtensa: update test_fp0_arith for DFPU
DFPU arithmetic opcodes update FSR flags. Add FSR parameters and expected FSR register values for the arithmetic tests. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>master
Max Filippov
parent
6ac269c33c
commit
e95ef43181
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@ -0,0 +1,142 @@
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#if XCHAL_HAVE_DFP || XCHAL_HAVE_FP_DIV
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#define DFPU 1
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#else
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#define DFPU 0
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#endif
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#define FCR_RM_NEAREST 0
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#define FCR_RM_TRUNC 1
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#define FCR_RM_CEIL 2
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#define FCR_RM_FLOOR 3
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#define FSR__ 0x00000000
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#define FSR_I 0x00000080
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#define FSR_U 0x00000100
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#define FSR_O 0x00000200
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#define FSR_Z 0x00000400
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#define FSR_V 0x00000800
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#define FSR_UI (FSR_U | FSR_I)
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#define FSR_OI (FSR_O | FSR_I)
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#define F32_0 0x00000000
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#define F32_0_5 0x3f000000
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#define F32_1 0x3f800000
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#define F32_MAX 0x7f7fffff
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#define F32_PINF 0x7f800000
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#define F32_NINF 0xff800000
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#define F32_DNAN 0x7fc00000
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#define F32_SNAN(v) (0x7f800000 | (v))
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#define F32_QNAN(v) (0x7fc00000 | (v))
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#define F32_MINUS 0x80000000
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#define F64_0 0x0000000000000000
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#define F64_MIN_NORM 0x0010000000000000
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#define F64_1 0x3ff0000000000000
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#define F64_MAX_2 0x7fe0000000000000
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#define F64_MAX 0x7fefffffffffffff
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#define F64_PINF 0x7ff0000000000000
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#define F64_NINF 0xfff0000000000000
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#define F64_DNAN 0x7ff8000000000000
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#define F64_SNAN(v) (0x7ff0000000000000 | (v))
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#define F64_QNAN(v) (0x7ff8000000000000 | (v))
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#define F64_MINUS 0x8000000000000000
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.macro test_op1_rm op, fr0, fr1, v0, r, sr
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movi a2, 0
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wur a2, fsr
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movfp \fr0, \v0
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\op \fr1, \fr0
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check_res \fr1, \r, \sr
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.endm
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.macro test_op2_rm op, fr0, fr1, fr2, v0, v1, r, sr
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movi a2, 0
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wur a2, fsr
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movfp \fr0, \v0
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movfp \fr1, \v1
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\op \fr2, \fr0, \fr1
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check_res \fr2, \r, \sr
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.endm
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.macro test_op3_rm op, fr0, fr1, fr2, fr3, v0, v1, v2, r, sr
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movi a2, 0
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wur a2, fsr
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movfp \fr0, \v0
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movfp \fr1, \v1
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movfp \fr2, \v2
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\op \fr0, \fr1, \fr2
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check_res \fr3, \r, \sr
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.endm
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.macro test_op1_ex op, fr0, fr1, v0, rm, r, sr
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movi a2, \rm
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wur a2, fcr
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test_op1_rm \op, \fr0, \fr1, \v0, \r, \sr
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movi a2, (\rm) | 0x7c
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wur a2, fcr
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test_op1_rm \op, \fr0, \fr1, \v0, \r, \sr
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.endm
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.macro test_op2_ex op, fr0, fr1, fr2, v0, v1, rm, r, sr
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movi a2, \rm
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wur a2, fcr
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test_op2_rm \op, \fr0, \fr1, \fr2, \v0, \v1, \r, \sr
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movi a2, (\rm) | 0x7c
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wur a2, fcr
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test_op2_rm \op, \fr0, \fr1, \fr2, \v0, \v1, \r, \sr
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.endm
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.macro test_op3_ex op, fr0, fr1, fr2, fr3, v0, v1, v2, rm, r, sr
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movi a2, \rm
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wur a2, fcr
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test_op3_rm \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, \r, \sr
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movi a2, (\rm) | 0x7c
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wur a2, fcr
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test_op3_rm \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, \r, \sr
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.endm
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.macro test_op1 op, fr0, fr1, v0, r0, r1, r2, r3, sr0, sr1, sr2, sr3
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test_op1_ex \op, \fr0, \fr1, \v0, 0, \r0, \sr0
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test_op1_ex \op, \fr0, \fr1, \v0, 1, \r1, \sr1
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test_op1_ex \op, \fr0, \fr1, \v0, 2, \r2, \sr2
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test_op1_ex \op, \fr0, \fr1, \v0, 3, \r3, \sr3
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.endm
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.macro test_op2 op, fr0, fr1, fr2, v0, v1, r0, r1, r2, r3, sr0, sr1, sr2, sr3
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test_op2_ex \op, \fr0, \fr1, \fr2, \v0, \v1, 0, \r0, \sr0
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test_op2_ex \op, \fr0, \fr1, \fr2, \v0, \v1, 1, \r1, \sr1
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test_op2_ex \op, \fr0, \fr1, \fr2, \v0, \v1, 2, \r2, \sr2
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test_op2_ex \op, \fr0, \fr1, \fr2, \v0, \v1, 3, \r3, \sr3
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.endm
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.macro test_op3 op, fr0, fr1, fr2, fr3, v0, v1, v2, r0, r1, r2, r3, sr0, sr1, sr2, sr3
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test_op3_ex \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, 0, \r0, \sr0
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test_op3_ex \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, 1, \r1, \sr1
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test_op3_ex \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, 2, \r2, \sr2
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test_op3_ex \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, 3, \r3, \sr3
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.endm
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.macro test_op2_cpe op
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set_vector kernel, 2f
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movi a2, 0
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wsr a2, cpenable
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1:
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\op f2, f0, f1
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test_fail
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2:
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rsr a2, excvaddr
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movi a3, 1b
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assert eq, a2, a3
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rsr a2, exccause
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movi a3, 32
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assert eq, a2, a3
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set_vector kernel, 0
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movi a2, 1
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wsr a2, cpenable
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.endm
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@ -1,4 +1,5 @@
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#include "macros.inc"
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#include "macros.inc"
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#include "fpu.h"
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test_suite fp0_arith
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test_suite fp0_arith
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@ -9,84 +10,18 @@ test_suite fp0_arith
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wfr \fr, a2
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wfr \fr, a2
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.endm
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.endm
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.macro check_res fr, r
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.macro check_res fr, r, sr
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rfr a2, \fr
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rfr a2, \fr
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dump a2
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dump a2
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movi a3, \r
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movi a3, \r
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assert eq, a2, a3
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assert eq, a2, a3
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rur a2, fsr
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rur a2, fsr
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#if DFPU
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movi a3, \sr
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assert eq, a2, a3
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#else
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assert eqi, a2, 0
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assert eqi, a2, 0
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.endm
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#endif
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.macro test_op2_rm op, fr0, fr1, fr2, v0, v1, r
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movi a2, 0
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wur a2, fsr
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movfp \fr0, \v0
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movfp \fr1, \v1
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\op \fr2, \fr0, \fr1
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check_res \fr2, \r
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.endm
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.macro test_op3_rm op, fr0, fr1, fr2, fr3, v0, v1, v2, r
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movi a2, 0
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wur a2, fsr
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movfp \fr0, \v0
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movfp \fr1, \v1
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movfp \fr2, \v2
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\op \fr0, \fr1, \fr2
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check_res \fr3, \r
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.endm
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.macro test_op2_ex op, fr0, fr1, fr2, v0, v1, rm, r
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movi a2, \rm
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wur a2, fcr
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test_op2_rm \op, \fr0, \fr1, \fr2, \v0, \v1, \r
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movi a2, (\rm) | 0x7c
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wur a2, fcr
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test_op2_rm \op, \fr0, \fr1, \fr2, \v0, \v1, \r
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.endm
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.macro test_op3_ex op, fr0, fr1, fr2, fr3, v0, v1, v2, rm, r
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movi a2, \rm
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wur a2, fcr
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test_op3_rm \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, \r
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movi a2, (\rm) | 0x7c
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wur a2, fcr
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test_op3_rm \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, \r
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.endm
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.macro test_op2 op, fr0, fr1, fr2, v0, v1, r0, r1, r2, r3
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test_op2_ex \op, \fr0, \fr1, \fr2, \v0, \v1, 0, \r0
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test_op2_ex \op, \fr0, \fr1, \fr2, \v0, \v1, 1, \r1
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test_op2_ex \op, \fr0, \fr1, \fr2, \v0, \v1, 2, \r2
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test_op2_ex \op, \fr0, \fr1, \fr2, \v0, \v1, 3, \r3
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.endm
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.macro test_op3 op, fr0, fr1, fr2, fr3, v0, v1, v2, r0, r1, r2, r3
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test_op3_ex \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, 0, \r0
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test_op3_ex \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, 1, \r1
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test_op3_ex \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, 2, \r2
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test_op3_ex \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, 3, \r3
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.endm
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.macro test_op2_cpe op
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set_vector kernel, 2f
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movi a2, 0
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wsr a2, cpenable
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1:
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\op f2, f0, f1
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test_fail
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2:
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rsr a2, excvaddr
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movi a3, 1b
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assert eq, a2, a3
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rsr a2, exccause
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movi a3, 32
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assert eq, a2, a3
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set_vector kernel, 0
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movi a2, 1
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wsr a2, cpenable
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.endm
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.endm
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test add_s
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test add_s
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@ -94,78 +29,127 @@ test add_s
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wsr a2, cpenable
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wsr a2, cpenable
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test_op2 add.s, f0, f1, f2, 0x3fc00000, 0x34400000, \
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test_op2 add.s, f0, f1, f2, 0x3fc00000, 0x34400000, \
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0x3fc00002, 0x3fc00001, 0x3fc00002, 0x3fc00001
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0x3fc00002, 0x3fc00001, 0x3fc00002, 0x3fc00001, \
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FSR_I, FSR_I, FSR_I, FSR_I
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test_op2 add.s, f3, f4, f5, 0x3fc00000, 0x34a00000, \
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test_op2 add.s, f3, f4, f5, 0x3fc00000, 0x34a00000, \
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0x3fc00002, 0x3fc00002, 0x3fc00003, 0x3fc00002
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0x3fc00002, 0x3fc00002, 0x3fc00003, 0x3fc00002, \
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FSR_I, FSR_I, FSR_I, FSR_I
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/* MAX_FLOAT + MAX_FLOAT = +inf/MAX_FLOAT */
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/* MAX_FLOAT + MAX_FLOAT = +inf/MAX_FLOAT */
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test_op2 add.s, f6, f7, f8, 0x7f7fffff, 0x7f7fffff, \
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test_op2 add.s, f6, f7, f8, 0x7f7fffff, 0x7f7fffff, \
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0x7f800000, 0x7f7fffff, 0x7f800000, 0x7f7fffff
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0x7f800000, 0x7f7fffff, 0x7f800000, 0x7f7fffff, \
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FSR_OI, FSR_OI, FSR_OI, FSR_OI
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test_end
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test_end
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test add_s_inf
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test add_s_inf
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/* 1 + +inf = +inf */
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/* 1 + +inf = +inf */
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test_op2 add.s, f6, f7, f8, 0x3fc00000, 0x7f800000, \
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test_op2 add.s, f6, f7, f8, 0x3fc00000, 0x7f800000, \
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0x7f800000, 0x7f800000, 0x7f800000, 0x7f800000
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0x7f800000, 0x7f800000, 0x7f800000, 0x7f800000, \
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FSR__, FSR__, FSR__, FSR__
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/* +inf + -inf = default NaN */
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/* +inf + -inf = default NaN */
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test_op2 add.s, f0, f1, f2, 0x7f800000, 0xff800000, \
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test_op2 add.s, f0, f1, f2, 0x7f800000, 0xff800000, \
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0x7fc00000, 0x7fc00000, 0x7fc00000, 0x7fc00000
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0x7fc00000, 0x7fc00000, 0x7fc00000, 0x7fc00000, \
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FSR_V, FSR_V, FSR_V, FSR_V
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test_end
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test_end
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test add_s_nan
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#if DFPU
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/* 1 + NaN = NaN */
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test add_s_nan_dfpu
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/* 1 + QNaN = QNaN */
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test_op2 add.s, f9, f10, f11, 0x3fc00000, 0x7fc00001, \
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test_op2 add.s, f9, f10, f11, 0x3fc00000, 0x7fc00001, \
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0x7fc00001, 0x7fc00001, 0x7fc00001, 0x7fc00001
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0x7fc00001, 0x7fc00001, 0x7fc00001, 0x7fc00001, \
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FSR__, FSR__, FSR__, FSR__
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/* 1 + SNaN = QNaN */
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test_op2 add.s, f12, f13, f14, 0x3fc00000, 0x7f800001, \
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test_op2 add.s, f12, f13, f14, 0x3fc00000, 0x7f800001, \
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0x7f800001, 0x7f800001, 0x7f800001, 0x7f800001
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0x7fc00001, 0x7fc00001, 0x7fc00001, 0x7fc00001, \
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FSR_V, FSR_V, FSR_V, FSR_V
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/* NaN1 + NaN2 = NaN1 */
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/* SNaN1 + SNaN2 = QNaN2 */
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test_op2 add.s, f15, f0, f1, 0x7f800001, 0x7fbfffff, \
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test_op2 add.s, f15, f0, f1, 0x7f800001, 0x7fbfffff, \
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0x7f800001, 0x7f800001, 0x7f800001, 0x7f800001
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0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff, \
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FSR_V, FSR_V, FSR_V, FSR_V
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test_op2 add.s, f2, f3, f4, 0x7fbfffff, 0x7f800001, \
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test_op2 add.s, f2, f3, f4, 0x7fbfffff, 0x7f800001, \
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0x7fbfffff, 0x7fbfffff, 0x7fbfffff, 0x7fbfffff
|
0x7fc00001, 0x7fc00001, 0x7fc00001, 0x7fc00001, \
|
||||||
|
FSR_V, FSR_V, FSR_V, FSR_V
|
||||||
|
/* QNaN1 + SNaN2 = QNaN2 */
|
||||||
test_op2 add.s, f5, f6, f7, 0x7fc00001, 0x7fbfffff, \
|
test_op2 add.s, f5, f6, f7, 0x7fc00001, 0x7fbfffff, \
|
||||||
0x7fc00001, 0x7fc00001, 0x7fc00001, 0x7fc00001
|
0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff, \
|
||||||
|
FSR_V, FSR_V, FSR_V, FSR_V
|
||||||
|
/* SNaN1 + QNaN2 = QNaN2 */
|
||||||
test_op2 add.s, f8, f9, f10, 0x7fbfffff, 0x7fc00001, \
|
test_op2 add.s, f8, f9, f10, 0x7fbfffff, 0x7fc00001, \
|
||||||
0x7fbfffff, 0x7fbfffff, 0x7fbfffff, 0x7fbfffff
|
0x7fc00001, 0x7fc00001, 0x7fc00001, 0x7fc00001, \
|
||||||
|
FSR_V, FSR_V, FSR_V, FSR_V
|
||||||
test_end
|
test_end
|
||||||
|
#else
|
||||||
|
test add_s_nan_fpu2k
|
||||||
|
/* 1 + QNaN = QNaN */
|
||||||
|
test_op2 add.s, f9, f10, f11, 0x3fc00000, 0x7fc00001, \
|
||||||
|
0x7fc00001, 0x7fc00001, 0x7fc00001, 0x7fc00001, \
|
||||||
|
FSR__, FSR__, FSR__, FSR__
|
||||||
|
/* 1 + SNaN = SNaN */
|
||||||
|
test_op2 add.s, f12, f13, f14, 0x3fc00000, 0x7f800001, \
|
||||||
|
0x7f800001, 0x7f800001, 0x7f800001, 0x7f800001, \
|
||||||
|
FSR__, FSR__, FSR__, FSR__
|
||||||
|
/* SNaN1 + SNaN2 = SNaN1 */
|
||||||
|
test_op2 add.s, f15, f0, f1, 0x7f800001, 0x7fbfffff, \
|
||||||
|
0x7f800001, 0x7f800001, 0x7f800001, 0x7f800001, \
|
||||||
|
FSR__, FSR__, FSR__, FSR__
|
||||||
|
test_op2 add.s, f2, f3, f4, 0x7fbfffff, 0x7f800001, \
|
||||||
|
0x7fbfffff, 0x7fbfffff, 0x7fbfffff, 0x7fbfffff, \
|
||||||
|
FSR__, FSR__, FSR__, FSR__
|
||||||
|
/* QNaN1 + SNaN2 = QNaN1 */
|
||||||
|
test_op2 add.s, f5, f6, f7, 0x7fc00001, 0x7fbfffff, \
|
||||||
|
0x7fc00001, 0x7fc00001, 0x7fc00001, 0x7fc00001, \
|
||||||
|
FSR__, FSR__, FSR__, FSR__
|
||||||
|
/* SNaN1 + QNaN2 = SNaN1 */
|
||||||
|
test_op2 add.s, f8, f9, f10, 0x7fbfffff, 0x7fc00001, \
|
||||||
|
0x7fbfffff, 0x7fbfffff, 0x7fbfffff, 0x7fbfffff, \
|
||||||
|
FSR__, FSR__, FSR__, FSR__
|
||||||
|
test_end
|
||||||
|
#endif
|
||||||
|
|
||||||
test sub_s
|
test sub_s
|
||||||
test_op2 sub.s, f0, f1, f0, 0x3f800001, 0x33800000, \
|
test_op2 sub.s, f0, f1, f0, 0x3f800001, 0x33800000, \
|
||||||
0x3f800000, 0x3f800000, 0x3f800001, 0x3f800000
|
0x3f800000, 0x3f800000, 0x3f800001, 0x3f800000, \
|
||||||
|
FSR_I, FSR_I, FSR_I, FSR_I
|
||||||
test_op2 sub.s, f0, f1, f1, 0x3f800002, 0x33800000, \
|
test_op2 sub.s, f0, f1, f1, 0x3f800002, 0x33800000, \
|
||||||
0x3f800002, 0x3f800001, 0x3f800002, 0x3f800001
|
0x3f800002, 0x3f800001, 0x3f800002, 0x3f800001, \
|
||||||
|
FSR_I, FSR_I, FSR_I, FSR_I
|
||||||
|
|
||||||
/* norm - norm = denorm */
|
/* norm - norm = denorm */
|
||||||
test_op2 sub.s, f6, f7, f8, 0x00800001, 0x00800000, \
|
test_op2 sub.s, f6, f7, f8, 0x00800001, 0x00800000, \
|
||||||
0x00000001, 0x00000001, 0x00000001, 0x00000001
|
0x00000001, 0x00000001, 0x00000001, 0x00000001, \
|
||||||
|
FSR__, FSR__, FSR__, FSR__
|
||||||
test_end
|
test_end
|
||||||
|
|
||||||
test mul_s
|
test mul_s
|
||||||
test_op2 mul.s, f0, f1, f2, 0x3f800001, 0x3f800001, \
|
test_op2 mul.s, f0, f1, f2, 0x3f800001, 0x3f800001, \
|
||||||
0x3f800002, 0x3f800002, 0x3f800003, 0x3f800002
|
0x3f800002, 0x3f800002, 0x3f800003, 0x3f800002, \
|
||||||
|
FSR_I, FSR_I, FSR_I, FSR_I
|
||||||
/* MAX_FLOAT/2 * MAX_FLOAT/2 = +inf/MAX_FLOAT */
|
/* MAX_FLOAT/2 * MAX_FLOAT/2 = +inf/MAX_FLOAT */
|
||||||
test_op2 mul.s, f6, f7, f8, 0x7f000000, 0x7f000000, \
|
test_op2 mul.s, f6, f7, f8, 0x7f000000, 0x7f000000, \
|
||||||
0x7f800000, 0x7f7fffff, 0x7f800000, 0x7f7fffff
|
0x7f800000, 0x7f7fffff, 0x7f800000, 0x7f7fffff, \
|
||||||
|
FSR_OI, FSR_OI, FSR_OI, FSR_OI
|
||||||
/* min norm * min norm = 0/denorm */
|
/* min norm * min norm = 0/denorm */
|
||||||
test_op2 mul.s, f6, f7, f8, 0x00800001, 0x00800000, \
|
test_op2 mul.s, f6, f7, f8, 0x00800001, 0x00800000, \
|
||||||
0x00000000, 0x00000000, 0x00000001, 0x00000000
|
0x00000000, 0x00000000, 0x00000001, 0x00000000, \
|
||||||
|
FSR_UI, FSR_UI, FSR_UI, FSR_UI
|
||||||
/* inf * 0 = default NaN */
|
/* inf * 0 = default NaN */
|
||||||
test_op2 mul.s, f6, f7, f8, 0x7f800000, 0x00000000, \
|
test_op2 mul.s, f6, f7, f8, 0x7f800000, 0x00000000, \
|
||||||
0x7fc00000, 0x7fc00000, 0x7fc00000, 0x7fc00000
|
0x7fc00000, 0x7fc00000, 0x7fc00000, 0x7fc00000, \
|
||||||
|
FSR_V, FSR_V, FSR_V, FSR_V
|
||||||
test_end
|
test_end
|
||||||
|
|
||||||
test madd_s
|
test madd_s
|
||||||
test_op3 madd.s, f0, f1, f2, f0, 0, 0x3f800001, 0x3f800001, \
|
test_op3 madd.s, f0, f1, f2, f0, 0, 0x3f800001, 0x3f800001, \
|
||||||
0x3f800002, 0x3f800002, 0x3f800003, 0x3f800002
|
0x3f800002, 0x3f800002, 0x3f800003, 0x3f800002, \
|
||||||
|
FSR_I, FSR_I, FSR_I, FSR_I
|
||||||
test_end
|
test_end
|
||||||
|
|
||||||
test msub_s
|
test msub_s
|
||||||
test_op3 msub.s, f0, f1, f2, f0, 0x3f800000, 0x3f800001, 0x3f800001, \
|
test_op3 msub.s, f0, f1, f2, f0, 0x3f800000, 0x3f800001, 0x3f800001, \
|
||||||
0xb4800000, 0xb4800000, 0xb4800000, 0xb4800001
|
0xb4800000, 0xb4800000, 0xb4800000, 0xb4800001, \
|
||||||
|
FSR_I, FSR_I, FSR_I, FSR_I
|
||||||
test_end
|
test_end
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue