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target/mips: Drop tcg_temp_free from tx79_translate.c 

Translators are no longer required to free tcg temporaries.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
master
Richard Henderson 2023-02-24 19:33:18 -10:00
parent fe5360215c
commit e9f27b3693
1 changed files with 0 additions and 41 deletions
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41
target/mips/tcg/tx79_translate.c
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@ -138,10 +138,6 @@ static bool trans_parallel_arith(DisasContext *ctx, arg_r *a,
gen_load_gpr_hi(ax, a->rs);
gen_load_gpr_hi(bx, a->rt);
gen_logic_i64(cpu_gpr_hi[a->rd], ax, bx);
tcg_temp_free(bx);
tcg_temp_free(ax);
return true;
}
@ -273,15 +269,6 @@ static bool trans_parallel_compare(DisasContext *ctx, arg_r *a,
tcg_gen_movcond_i64(cond, t2, t1, t0, c1, c0);
tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rd], t2, wlen * i, wlen);
}
tcg_temp_free(t2);
tcg_temp_free(t1);
tcg_temp_free(t0);
tcg_temp_free(bx);
tcg_temp_free(ax);
tcg_temp_free(c1);
tcg_temp_free(c0);
return true;
}
@ -362,10 +349,6 @@ static bool trans_LQ(DisasContext *ctx, arg_i *a)
tcg_gen_addi_i64(addr, addr, 8);
tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, MO_TEUQ);
gen_store_gpr_hi(t0, a->rt);
tcg_temp_free(t0);
tcg_temp_free(addr);
return true;
}
@ -389,10 +372,6 @@ static bool trans_SQ(DisasContext *ctx, arg_i *a)
tcg_gen_addi_i64(addr, addr, 8);
gen_load_gpr_hi(t0, a->rt);
tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, MO_TEUQ);
tcg_temp_free(addr);
tcg_temp_free(t0);
return true;
}
@ -458,11 +437,6 @@ static bool trans_PPACW(DisasContext *ctx, arg_r *a)
gen_load_gpr_hi(t0, a->rs); /* a1 */
tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], a0, t0, 32, 32);
tcg_temp_free(t0);
tcg_temp_free(b0);
tcg_temp_free(a0);
return true;
}
@ -506,10 +480,6 @@ static bool trans_PEXTLx(DisasContext *ctx, arg_r *a, unsigned wlen)
tcg_gen_shri_i64(bx, bx, wlen);
tcg_gen_shri_i64(ax, ax, wlen);
}
tcg_temp_free(bx);
tcg_temp_free(ax);
return true;
}
@ -541,10 +511,6 @@ static bool trans_PEXTLW(DisasContext *ctx, arg_r *a)
gen_load_gpr(ax, a->rs);
gen_load_gpr(bx, a->rt);
gen_pextw(cpu_gpr[a->rd], cpu_gpr_hi[a->rd], ax, bx);
tcg_temp_free(bx);
tcg_temp_free(ax);
return true;
}
@ -564,10 +530,6 @@ static bool trans_PEXTUW(DisasContext *ctx, arg_r *a)
gen_load_gpr_hi(ax, a->rs);
gen_load_gpr_hi(bx, a->rt);
gen_pextw(cpu_gpr[a->rd], cpu_gpr_hi[a->rd], ax, bx);
tcg_temp_free(bx);
tcg_temp_free(ax);
return true;
}
@ -678,8 +640,5 @@ static bool trans_PROT3W(DisasContext *ctx, arg_r *a)
tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rt], ax, 0, 32);
tcg_gen_rotri_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], 32);
tcg_temp_free(ax);
return true;
}