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dp8393x: Use long-word-aligned RRA pointers in 32-bit mode 

Section 3.4.1 of the datasheet says,

    The alignment of the RRA is confined to either word or long word
    boundaries, depending upon the data width mode. In 16-bit mode,
    the RRA must be aligned to a word boundary (A0 is always zero)
    and in 32-bit mode, the RRA is aligned to a long word boundary
    (A0 and A1 are always zero).

This constraint has been implemented for 16-bit mode; implement it
for 32-bit mode too.

Signed-off-by: Finn Thain <fthain@telegraphics.com.au>
Tested-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
master
Finn Thain 2020-01-29 20:27:49 +11:00 committed by Jason Wang
parent bae112b80c
commit ea2270279b
1 changed files with 6 additions and 2 deletions
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8
hw/net/dp8393x.c
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@ -665,12 +665,16 @@ static void dp8393x_write(void *opaque, hwaddr addr, uint64_t data,
qemu_flush_queued_packets(qemu_get_queue(s->nic));
}
break;
/* Ignore least significant bit */
/* The guest is required to store aligned pointers here */
case SONIC_RSA:
case SONIC_REA:
case SONIC_RRP:
case SONIC_RWP:
s->regs[reg] = val & 0xfffe;
if (s->regs[SONIC_DCR] & SONIC_DCR_DW) {
s->regs[reg] = val & 0xfffc;
} else {
s->regs[reg] = val & 0xfffe;
}
break;
/* Invert written value for some registers */
case SONIC_CRCT: