From ea4b07f7623c3863d86aad3d5718c28d39e1a1a9 Mon Sep 17 00:00:00 2001
From: ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162>
Date: Fri, 28 Dec 2007 12:35:05 +0000
Subject: [PATCH] Set FCR0.F64 for MIPS64R2-generic, by Richard Sandiford.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3865 c046a42c-6fe2-441c-8c8c-71466251a162
---
 target-mips/translate_init.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index 57666d4db7..72788e81c9 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -403,9 +403,9 @@ static mips_def_t mips_defs[] =
         .SYNCI_Step = 32,
         .CCRes = 2,
         .CP0_Status_rw_bitmask = 0x36FBFFFF,
-        .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) | (1 << FCR0_L) |
-                    (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) |
-                    (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
+        .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
+                    (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
+                    (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
         .SEGBITS = 42,
         /* The architectural limit is 59, but we have hardcoded 36 bit
            in some places...