mirror of https://github.com/proxmox/mirror_qemu
gdbstub: Infer number of core registers from XML
GDBFeature has the num_regs member so use it where applicable to remove magic numbers. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Message-Id: <20231213-gdb-v17-8-777047380591@daynix.com> [AJB: remove core reg check from microblaze read reg] Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240227144335.1196131-13-alex.bennee@linaro.org>master
parent
ee59fa1dd5
commit
ecd6f6a882
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@ -546,9 +546,12 @@ void gdb_init_cpu(CPUState *cpu)
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gdb_register_feature(cpu, 0,
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cc->gdb_read_register, cc->gdb_write_register,
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feature);
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cpu->gdb_num_regs = cpu->gdb_num_g_regs = feature->num_regs;
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}
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cpu->gdb_num_regs = cpu->gdb_num_g_regs = cc->gdb_num_core_regs;
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if (cc->gdb_num_core_regs) {
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cpu->gdb_num_regs = cpu->gdb_num_g_regs = cc->gdb_num_core_regs;
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}
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}
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void gdb_register_coprocessor(CPUState *cpu,
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@ -126,7 +126,8 @@ struct SysemuCPUOps;
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* @gdb_adjust_breakpoint: Callback for adjusting the address of a
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* breakpoint. Used by AVR to handle a gdb mis-feature with
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* its Harvard architecture split code and data.
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* @gdb_num_core_regs: Number of core registers accessible to GDB.
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* @gdb_num_core_regs: Number of core registers accessible to GDB or 0 to infer
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* from @gdb_core_xml_file.
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* @gdb_core_xml_file: File name for core registers GDB XML description.
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* @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop
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* before the insn which triggers a watchpoint rather than after it.
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@ -2515,7 +2515,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
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#ifndef CONFIG_USER_ONLY
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cc->sysemu_ops = &arm_sysemu_ops;
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#endif
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cc->gdb_num_core_regs = 26;
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cc->gdb_arch_name = arm_gdb_arch_name;
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cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml;
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cc->gdb_stop_before_watchpoint = true;
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@ -793,7 +793,6 @@ static void aarch64_cpu_class_init(ObjectClass *oc, void *data)
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cc->gdb_read_register = aarch64_cpu_gdb_read_register;
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cc->gdb_write_register = aarch64_cpu_gdb_write_register;
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cc->gdb_num_core_regs = 34;
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cc->gdb_core_xml_file = "aarch64-core.xml";
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cc->gdb_arch_name = aarch64_gdb_arch_name;
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@ -251,7 +251,6 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
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cc->gdb_read_register = avr_cpu_gdb_read_register;
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cc->gdb_write_register = avr_cpu_gdb_write_register;
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cc->gdb_adjust_breakpoint = avr_cpu_gdb_adjust_breakpoint;
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cc->gdb_num_core_regs = 35;
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cc->gdb_core_xml_file = "avr-cpu.xml";
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cc->tcg_ops = &avr_tcg_ops;
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}
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@ -362,7 +362,6 @@ static void hexagon_cpu_class_init(ObjectClass *c, void *data)
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cc->get_pc = hexagon_cpu_get_pc;
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cc->gdb_read_register = hexagon_gdb_read_register;
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cc->gdb_write_register = hexagon_gdb_write_register;
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cc->gdb_num_core_regs = TOTAL_PER_THREAD_REGS;
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cc->gdb_stop_before_watchpoint = true;
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cc->gdb_core_xml_file = "hexagon-core.xml";
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cc->disas_set_info = hexagon_cpu_disas_set_info;
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@ -7990,10 +7990,8 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
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cc->gdb_arch_name = x86_gdb_arch_name;
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#ifdef TARGET_X86_64
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cc->gdb_core_xml_file = "i386-64bit.xml";
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cc->gdb_num_core_regs = 66;
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#else
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cc->gdb_core_xml_file = "i386-32bit.xml";
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cc->gdb_num_core_regs = 50;
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#endif
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cc->disas_set_info = x86_disas_set_info;
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@ -815,7 +815,6 @@ static void loongarch32_cpu_class_init(ObjectClass *c, void *data)
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{
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CPUClass *cc = CPU_CLASS(c);
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cc->gdb_num_core_regs = 35;
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cc->gdb_core_xml_file = "loongarch-base32.xml";
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cc->gdb_arch_name = loongarch32_gdb_arch_name;
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}
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@ -829,7 +828,6 @@ static void loongarch64_cpu_class_init(ObjectClass *c, void *data)
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{
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CPUClass *cc = CPU_CLASS(c);
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cc->gdb_num_core_regs = 35;
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cc->gdb_core_xml_file = "loongarch-base64.xml";
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cc->gdb_arch_name = loongarch64_gdb_arch_name;
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}
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@ -570,7 +570,6 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
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#endif
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cc->disas_set_info = m68k_cpu_disas_set_info;
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cc->gdb_num_core_regs = 18;
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cc->tcg_ops = &m68k_tcg_ops;
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}
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@ -444,7 +444,6 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
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cc->sysemu_ops = &mb_sysemu_ops;
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#endif
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device_class_set_props(dc, mb_properties);
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cc->gdb_num_core_regs = 32 + 25;
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cc->gdb_core_xml_file = "microblaze-core.xml";
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cc->disas_set_info = mb_disas_set_info;
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@ -49,14 +49,9 @@ enum {
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int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
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{
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MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
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CPUClass *cc = CPU_GET_CLASS(cs);
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CPUMBState *env = &cpu->env;
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uint32_t val;
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if (n > cc->gdb_num_core_regs) {
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return 0;
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}
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switch (n) {
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case 1 ... 31:
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val = env->regs[n];
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@ -2352,7 +2352,6 @@ static void riscv_cpu_common_class_init(ObjectClass *c, void *data)
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cc->get_pc = riscv_cpu_get_pc;
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cc->gdb_read_register = riscv_cpu_gdb_read_register;
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cc->gdb_write_register = riscv_cpu_gdb_write_register;
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cc->gdb_num_core_regs = 33;
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cc->gdb_stop_before_watchpoint = true;
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cc->disas_set_info = riscv_cpu_disas_set_info;
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#ifndef CONFIG_USER_ONLY
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@ -221,7 +221,6 @@ static void rx_cpu_class_init(ObjectClass *klass, void *data)
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cc->gdb_write_register = rx_cpu_gdb_write_register;
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cc->disas_set_info = rx_cpu_disas_set_info;
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cc->gdb_num_core_regs = 26;
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cc->gdb_core_xml_file = "rx-core.xml";
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cc->tcg_ops = &rx_tcg_ops;
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}
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@ -368,7 +368,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
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s390_cpu_class_init_sysemu(cc);
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#endif
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cc->disas_set_info = s390_cpu_disas_set_info;
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cc->gdb_num_core_regs = S390_NUM_CORE_REGS;
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cc->gdb_core_xml_file = "s390x-core64.xml";
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cc->gdb_arch_name = s390_gdb_arch_name;
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@ -491,8 +491,6 @@ static inline void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc,
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#define S390_R13_REGNUM 15
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#define S390_R14_REGNUM 16
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#define S390_R15_REGNUM 17
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/* Total Core Registers. */
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#define S390_NUM_CORE_REGS 18
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static inline void setcc(S390CPU *cpu, uint64_t cc)
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{
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