mirror of https://github.com/proxmox/mirror_qemu
target/mips: Let CPUMIPSTLBContext::map_address() take MMUAccessType
get_seg_physical_address() calls CPUMIPSTLBContext::map_address() handlers passing a MMUAccessType type. Update the prototype handlers to take a MMUAccessType argument, as it is stricter than an integer. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20210128144125.3696119-14-f4bug@amsat.org>master
parent
67b663d6fa
commit
edbd4992fb
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@ -111,7 +111,7 @@ struct CPUMIPSTLBContext {
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uint32_t nb_tlb;
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uint32_t nb_tlb;
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uint32_t tlb_in_use;
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uint32_t tlb_in_use;
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int (*map_address)(struct CPUMIPSState *env, hwaddr *physical, int *prot,
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int (*map_address)(struct CPUMIPSState *env, hwaddr *physical, int *prot,
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target_ulong address, int rw);
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target_ulong address, MMUAccessType access_type);
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void (*helper_tlbwi)(struct CPUMIPSState *env);
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void (*helper_tlbwi)(struct CPUMIPSState *env);
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void (*helper_tlbwr)(struct CPUMIPSState *env);
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void (*helper_tlbwr)(struct CPUMIPSState *env);
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void (*helper_tlbp)(struct CPUMIPSState *env);
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void (*helper_tlbp)(struct CPUMIPSState *env);
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@ -126,11 +126,11 @@ struct CPUMIPSTLBContext {
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};
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};
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int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
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int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
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target_ulong address, int rw);
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target_ulong address, MMUAccessType access_type);
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int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
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int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
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target_ulong address, int rw);
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target_ulong address, MMUAccessType access_type);
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int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
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int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
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target_ulong address, int rw);
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target_ulong address, MMUAccessType access_type);
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void r4k_helper_tlbwi(CPUMIPSState *env);
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void r4k_helper_tlbwi(CPUMIPSState *env);
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void r4k_helper_tlbwr(CPUMIPSState *env);
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void r4k_helper_tlbwr(CPUMIPSState *env);
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void r4k_helper_tlbp(CPUMIPSState *env);
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void r4k_helper_tlbp(CPUMIPSState *env);
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@ -39,7 +39,7 @@ enum {
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/* no MMU emulation */
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/* no MMU emulation */
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int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
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int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
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target_ulong address, int rw)
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target_ulong address, MMUAccessType access_type)
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{
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{
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*physical = address;
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*physical = address;
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*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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@ -48,7 +48,7 @@ int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
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/* fixed mapping MMU emulation */
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/* fixed mapping MMU emulation */
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int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
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int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
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target_ulong address, int rw)
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target_ulong address, MMUAccessType access_type)
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{
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{
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if (address <= (int32_t)0x7FFFFFFFUL) {
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if (address <= (int32_t)0x7FFFFFFFUL) {
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if (!(env->CP0_Status & (1 << CP0St_ERL))) {
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if (!(env->CP0_Status & (1 << CP0St_ERL))) {
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@ -68,7 +68,7 @@ int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
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/* MIPS32/MIPS64 R4000-style MMU emulation */
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/* MIPS32/MIPS64 R4000-style MMU emulation */
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int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
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int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
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target_ulong address, int rw)
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target_ulong address, MMUAccessType access_type)
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{
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{
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uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
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uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
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uint32_t MMID = env->CP0_MemoryMapID;
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uint32_t MMID = env->CP0_MemoryMapID;
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@ -97,13 +97,13 @@ int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
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if (!(n ? tlb->V1 : tlb->V0)) {
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if (!(n ? tlb->V1 : tlb->V0)) {
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return TLBRET_INVALID;
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return TLBRET_INVALID;
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}
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}
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if (rw == MMU_INST_FETCH && (n ? tlb->XI1 : tlb->XI0)) {
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if (access_type == MMU_INST_FETCH && (n ? tlb->XI1 : tlb->XI0)) {
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return TLBRET_XI;
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return TLBRET_XI;
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}
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}
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if (rw == MMU_DATA_LOAD && (n ? tlb->RI1 : tlb->RI0)) {
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if (access_type == MMU_DATA_LOAD && (n ? tlb->RI1 : tlb->RI0)) {
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return TLBRET_RI;
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return TLBRET_RI;
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}
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}
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if (rw != MMU_DATA_STORE || (n ? tlb->D1 : tlb->D0)) {
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if (access_type != MMU_DATA_STORE || (n ? tlb->D1 : tlb->D0)) {
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*physical = tlb->PFN[n] | (address & (mask >> 1));
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*physical = tlb->PFN[n] | (address & (mask >> 1));
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*prot = PAGE_READ;
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*prot = PAGE_READ;
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if (n ? tlb->D1 : tlb->D0) {
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if (n ? tlb->D1 : tlb->D0) {
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