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hw/pci-bridge: Constify VMState 

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20231221031652.119827-46-richard.henderson@linaro.org>
master
Richard Henderson 2023-12-21 14:16:26 +11:00
parent 8e5e0890b7
commit f026c578eb
7 changed files with 7 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
hw/pci-bridge/gen_pcie_root_port.c
View File

@ -117,7 +117,7 @@ static const VMStateDescription vmstate_rp_dev = {
.version_id = 1,
.minimum_version_id = 1,
.post_load = pcie_cap_slot_post_load,
.fields = (VMStateField[]) {
.fields = (const VMStateField[]) {
VMSTATE_PCI_DEVICE(parent_obj.parent_obj.parent_obj, PCIESlot),
VMSTATE_STRUCT(parent_obj.parent_obj.parent_obj.exp.aer_log,
PCIESlot, 0, vmstate_pcie_aer_log, PCIEAERLog),

2
hw/pci-bridge/i82801b11.c
View File

@ -81,7 +81,7 @@ err_bridge:
static const VMStateDescription i82801b11_bridge_dev_vmstate = {
.name = "i82801b11_bridge",
.priority = MIG_PRI_PCI_BUS,
.fields = (VMStateField[]) {
.fields = (const VMStateField[]) {
VMSTATE_PCI_DEVICE(parent_obj, PCIBridge),
VMSTATE_END_OF_LIST()
}

2
hw/pci-bridge/ioh3420.c
View File

@ -88,7 +88,7 @@ static const VMStateDescription vmstate_ioh3420 = {
.version_id = 1,
.minimum_version_id = 1,
.post_load = pcie_cap_slot_post_load,
.fields = (VMStateField[]) {
.fields = (const VMStateField[]) {
VMSTATE_PCI_DEVICE(parent_obj.parent_obj.parent_obj, PCIESlot),
VMSTATE_STRUCT(parent_obj.parent_obj.parent_obj.exp.aer_log,
PCIESlot, 0, vmstate_pcie_aer_log, PCIEAERLog),

2
hw/pci-bridge/pci_bridge_dev.c
View File

@ -199,7 +199,7 @@ static bool pci_device_shpc_present(void *opaque, int version_id)
static const VMStateDescription pci_bridge_dev_vmstate = {
.name = "pci_bridge",
.priority = MIG_PRI_PCI_BUS,
.fields = (VMStateField[]) {
.fields = (const VMStateField[]) {
VMSTATE_PCI_DEVICE(parent_obj, PCIBridge),
SHPC_VMSTATE(shpc, PCIDevice, pci_device_shpc_present),
VMSTATE_END_OF_LIST()

2
hw/pci-bridge/pcie_pci_bridge.c
View File

@ -132,7 +132,7 @@ static Property pcie_pci_bridge_dev_properties[] = {
static const VMStateDescription pcie_pci_bridge_dev_vmstate = {
.name = TYPE_PCIE_PCI_BRIDGE_DEV,
.priority = MIG_PRI_PCI_BUS,
.fields = (VMStateField[]) {
.fields = (const VMStateField[]) {
VMSTATE_PCI_DEVICE(parent_obj, PCIBridge),
SHPC_VMSTATE(shpc, PCIDevice, NULL),
VMSTATE_END_OF_LIST()

2
hw/pci-bridge/xio3130_downstream.c
View File

@ -146,7 +146,7 @@ static const VMStateDescription vmstate_xio3130_downstream = {
.version_id = 1,
.minimum_version_id = 1,
.post_load = pcie_cap_slot_post_load,
.fields = (VMStateField[]) {
.fields = (const VMStateField[]) {
VMSTATE_PCI_DEVICE(parent_obj.parent_obj.parent_obj, PCIESlot),
VMSTATE_STRUCT(parent_obj.parent_obj.parent_obj.exp.aer_log,
PCIESlot, 0, vmstate_pcie_aer_log, PCIEAERLog),

2
hw/pci-bridge/xio3130_upstream.c
View File

@ -115,7 +115,7 @@ static const VMStateDescription vmstate_xio3130_upstream = {
.priority = MIG_PRI_PCI_BUS,
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
.fields = (const VMStateField[]) {
VMSTATE_PCI_DEVICE(parent_obj.parent_obj, PCIEPort),
VMSTATE_STRUCT(parent_obj.parent_obj.exp.aer_log, PCIEPort, 0,
vmstate_pcie_aer_log, PCIEAERLog),