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target/riscv: fix start byte for vmv<nf>r.v when vstart != 0 

The spec for vmv<nf>r.v says: 'the instructions operate as if EEW=SEW,
EMUL = NREG, effective length evl= EMUL * VLEN/SEW.'

So the start byte for vstart != 0 should take sew into account

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220330021316.18223-1-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
master
Weiwei Li 2022-03-30 10:13:16 +08:00 committed by Alistair Francis
parent a775398be2
commit f06193c40b
1 changed files with 5 additions and 3 deletions
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8
target/riscv/vector_helper.c
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@ -4890,13 +4890,15 @@ GEN_VEXT_VCOMPRESS_VM(vcompress_vm_d, uint64_t, H8)
/* Vector Whole Register Move */
void HELPER(vmvr_v)(void *vd, void *vs2, CPURISCVState *env, uint32_t desc)
{
/* EEW = 8 */
/* EEW = SEW */
uint32_t maxsz = simd_maxsz(desc);
uint32_t i = env->vstart;
uint32_t sewb = 1 << FIELD_EX64(env->vtype, VTYPE, VSEW);
uint32_t startb = env->vstart * sewb;
uint32_t i = startb;
memcpy((uint8_t *)vd + H1(i),
(uint8_t *)vs2 + H1(i),
maxsz - env->vstart);
maxsz - startb);
env->vstart = 0;
}