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Move cpu_has_work and cpu_pc_from_tb to cpu.h 

Move functions cpu_has_work() and cpu_pc_from_tb() from exec.h to cpu.h. This is
needed by later patches.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
master
Blue Swirl 2011-05-21 07:10:23 +00:00
parent f3e270377a
commit f081c76ccf
28 changed files with 213 additions and 198 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
exec-all.h
View File

@ -40,6 +40,7 @@ typedef ram_addr_t tb_page_addr_t;
#define DISAS_UPDATE 2 /* cpu state was modified dynamically */
#define DISAS_TB_JUMP 3 /* only pc was modified statically */
struct TranslationBlock;
typedef struct TranslationBlock TranslationBlock;
/* XXX: make safe guess about sizes */

22
target-alpha/cpu.h
View File

@ -492,4 +492,26 @@ static inline void cpu_set_tls(CPUState *env, target_ulong newtls)
}
#endif
static inline bool cpu_has_work(CPUState *env)
{
/* Here we are checking to see if the CPU should wake up from HALT.
We will have gotten into this state only for WTINT from PALmode. */
/* ??? I'm not sure how the IPL state works with WTINT to keep a CPU
asleep even if (some) interrupts have been asserted. For now,
assume that if a CPU really wants to stay asleep, it will mask
interrupts at the chipset level, which will prevent these bits
from being set in the first place. */
return env->interrupt_request & (CPU_INTERRUPT_HARD
| CPU_INTERRUPT_TIMER
| CPU_INTERRUPT_SMP
| CPU_INTERRUPT_MCHK);
}
#include "exec-all.h"
static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
{
env->pc = tb->pc;
}
#endif /* !defined (__CPU_ALPHA_H__) */

20
target-alpha/exec.h
View File

@ -37,24 +37,4 @@ register struct CPUAlphaState *env asm(AREG0);
#include "softmmu_exec.h"
#endif /* !defined(CONFIG_USER_ONLY) */
static inline bool cpu_has_work(CPUState *env)
{
/* Here we are checking to see if the CPU should wake up from HALT.
We will have gotten into this state only for WTINT from PALmode. */
/* ??? I'm not sure how the IPL state works with WTINT to keep a CPU
asleep even if (some) interrupts have been asserted. For now,
assume that if a CPU really wants to stay asleep, it will mask
interrupts at the chipset level, which will prevent these bits
from being set in the first place. */
return env->interrupt_request & (CPU_INTERRUPT_HARD
| CPU_INTERRUPT_TIMER
| CPU_INTERRUPT_SMP
| CPU_INTERRUPT_MCHK);
}
static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
{
env->pc = tb->pc;
}
#endif /* !defined (__ALPHA_EXEC_H__) */

13
target-arm/cpu.h
View File

@ -512,4 +512,17 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
}
}
static inline bool cpu_has_work(CPUState *env)
{
return env->interrupt_request &
(CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
}
#include "exec-all.h"
static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
{
env->regs[15] = tb->pc;
}
#endif

12
target-arm/exec.h
View File

@ -24,20 +24,8 @@ register struct CPUARMState *env asm(AREG0);
#include "cpu.h"
#include "exec-all.h"
static inline bool cpu_has_work(CPUState *env)
{
return env->interrupt_request &
(CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
}
#if !defined(CONFIG_USER_ONLY)
#include "softmmu_exec.h"
#endif
void raise_exception(int);
static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
{
env->regs[15] = tb->pc;
}

11
target-cris/cpu.h
View File

@ -268,4 +268,15 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
#define cpu_list cris_cpu_list
void cris_cpu_list(FILE *f, fprintf_function cpu_fprintf);
static inline bool cpu_has_work(CPUState *env)
{
return env->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
}
#include "exec-all.h"
static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
{
env->pc = tb->pc;
}
#endif

11
target-cris/exec.h
View File

@ -27,14 +27,3 @@ register struct CPUCRISState *env asm(AREG0);
#if !defined(CONFIG_USER_ONLY)
#include "softmmu_exec.h"
#endif
static inline bool cpu_has_work(CPUState *env)
{
return env->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
}
static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
{
env->pc = tb->pc;
}

47
target-i386/cpu.h
View File

@ -957,6 +957,36 @@ static inline int cpu_mmu_index (CPUState *env)
return (env->hflags & HF_CPL_MASK) == 3 ? 1 : 0;
}
#undef EAX
#define EAX (env->regs[R_EAX])
#undef ECX
#define ECX (env->regs[R_ECX])
#undef EDX
#define EDX (env->regs[R_EDX])
#undef EBX
#define EBX (env->regs[R_EBX])
#undef ESP
#define ESP (env->regs[R_ESP])
#undef EBP
#define EBP (env->regs[R_EBP])
#undef ESI
#define ESI (env->regs[R_ESI])
#undef EDI
#define EDI (env->regs[R_EDI])
#undef EIP
#define EIP (env->eip)
#define DF (env->df)
#define CC_SRC (env->cc_src)
#define CC_DST (env->cc_dst)
#define CC_OP (env->cc_op)
/* float macros */
#define FT0 (env->ft0)
#define ST0 (env->fpregs[env->fpstt].d)
#define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d)
#define ST1 ST(1)
/* translate.c */
void optimize_flags_init(void);
@ -981,6 +1011,23 @@ static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
#include "hw/apic.h"
#endif
static inline bool cpu_has_work(CPUState *env)
{
return ((env->interrupt_request & CPU_INTERRUPT_HARD) &&
(env->eflags & IF_MASK)) ||
(env->interrupt_request & (CPU_INTERRUPT_NMI |
CPU_INTERRUPT_INIT |
CPU_INTERRUPT_SIPI |
CPU_INTERRUPT_MCE));
}
#include "exec-all.h"
static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
{
env->eip = tb->pc - tb->cs_base;
}
static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
target_ulong *cs_base, int *flags)
{

46
target-i386/exec.h
View File

@ -33,36 +33,6 @@ register struct CPUX86State *env asm(AREG0);
#include "qemu-common.h"
#include "qemu-log.h"
#undef EAX
#define EAX (env->regs[R_EAX])
#undef ECX
#define ECX (env->regs[R_ECX])
#undef EDX
#define EDX (env->regs[R_EDX])
#undef EBX
#define EBX (env->regs[R_EBX])
#undef ESP
#define ESP (env->regs[R_ESP])
#undef EBP
#define EBP (env->regs[R_EBP])
#undef ESI
#define ESI (env->regs[R_ESI])
#undef EDI
#define EDI (env->regs[R_EDI])
#undef EIP
#define EIP (env->eip)
#define DF (env->df)
#define CC_SRC (env->cc_src)
#define CC_DST (env->cc_dst)
#define CC_OP (env->cc_op)
/* float macros */
#define FT0 (env->ft0)
#define ST0 (env->fpregs[env->fpstt].d)
#define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d)
#define ST1 ST(1)
#include "cpu.h"
#include "exec-all.h"
@ -160,16 +130,6 @@ static inline void load_eflags(int eflags, int update_mask)
(eflags & update_mask) | 0x2;
}
static inline bool cpu_has_work(CPUState *env)
{
return ((env->interrupt_request & CPU_INTERRUPT_HARD) &&
(env->eflags & IF_MASK)) ||
(env->interrupt_request & (CPU_INTERRUPT_NMI |
CPU_INTERRUPT_INIT |
CPU_INTERRUPT_SIPI |
CPU_INTERRUPT_MCE));
}
/* load efer and update the corresponding hflags. XXX: do consistency
checks with cpuid bits ? */
static inline void cpu_load_efer(CPUState *env, uint64_t val)
@ -181,9 +141,3 @@ static inline void cpu_load_efer(CPUState *env, uint64_t val)
if (env->efer & MSR_EFER_SVME)
env->hflags |= HF_SVME_MASK;
}
static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
{
env->eip = tb->pc - tb->cs_base;
}

13
target-lm32/cpu.h
View File

@ -241,4 +241,17 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
*cs_base = 0;
*flags = 0;
}
static inline bool cpu_has_work(CPUState *env)
{
return env->interrupt_request & CPU_INTERRUPT_HARD;
}
#include "exec-all.h"
static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
{
env->pc = tb->pc;
}
#endif

11
target-lm32/exec.h
View File

@ -24,11 +24,6 @@ register struct CPULM32State *env asm(AREG0);
#include "cpu.h"
#include "exec-all.h"
static inline bool cpu_has_work(CPUState *env)
{
return env->interrupt_request & CPU_INTERRUPT_HARD;
}
static inline int cpu_halted(CPUState *env)
{
if (!env->halted) {
@ -42,9 +37,3 @@ static inline int cpu_halted(CPUState *env)
}
return EXCP_HALTED;
}
static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
{
env->pc = tb->pc;
}

12
target-m68k/cpu.h
View File

@ -255,4 +255,16 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
| ((env->macsr >> 4) & 0xf); /* Bits 0-3 */
}
static inline bool cpu_has_work(CPUState *env)
{
return env->interrupt_request & CPU_INTERRUPT_HARD;
}
#include "exec-all.h"
static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
{
env->pc = tb->pc;
}
#endif

11
target-m68k/exec.h
View File

@ -27,14 +27,3 @@ register struct CPUM68KState *env asm(AREG0);
#if !defined(CONFIG_USER_ONLY)
#include "softmmu_exec.h"
#endif
static inline bool cpu_has_work(CPUState *env)
{
return env->interrupt_request & (CPU_INTERRUPT_HARD);
}
static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
{
env->pc = tb->pc;
}

13
target-microblaze/cpu.h
View File

@ -350,4 +350,17 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
int is_asi, int size);
#endif
static inline bool cpu_has_work(CPUState *env)
{
return env->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
}
#include "exec-all.h"
static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
{
env->sregs[SR_PC] = tb->pc;
}
#endif

11
target-microblaze/exec.h
View File

@ -26,14 +26,3 @@ register struct CPUMBState *env asm(AREG0);
#if !defined(CONFIG_USER_ONLY)
#include "softmmu_exec.h"
#endif
static inline bool cpu_has_work(CPUState *env)
{
return env->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
}
static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
{
env->sregs[SR_PC] = tb->pc;
}

24
target-mips/cpu.h
View File

@ -656,4 +656,28 @@ static inline void cpu_set_tls(CPUState *env, target_ulong newtls)
env->tls_value = newtls;
}
static inline int cpu_has_work(CPUState *env)
{
int has_work = 0;
/* It is implementation dependent if non-enabled interrupts
wake-up the CPU, however most of the implementations only
check for interrupts that can be taken. */
if ((env->interrupt_request & CPU_INTERRUPT_HARD) &&
cpu_mips_hw_interrupts_pending(env)) {
has_work = 1;
}
return has_work;
}
#include "exec-all.h"
static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
{
env->active_tc.PC = tb->pc;
env->hflags &= ~MIPS_HFLAG_BMASK;
env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
}
#endif /* !defined (__MIPS_CPU_H__) */

22
target-mips/exec.h
View File

@ -17,21 +17,6 @@ register struct CPUMIPSState *env asm(AREG0);
#include "softmmu_exec.h"
#endif /* !defined(CONFIG_USER_ONLY) */
static inline bool cpu_has_work(CPUState *env)
{
int has_work = 0;
/* It is implementation dependent if non-enabled interrupts
wake-up the CPU, however most of the implementations only
check for interrupts that can be taken. */
if ((env->interrupt_request & CPU_INTERRUPT_HARD) &&
cpu_mips_hw_interrupts_pending(env)) {
has_work = 1;
}
return has_work;
}
static inline void compute_hflags(CPUState *env)
{
env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
@ -73,11 +58,4 @@ static inline void compute_hflags(CPUState *env)
}
}
static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
{
env->active_tc.PC = tb->pc;
env->hflags &= ~MIPS_HFLAG_BMASK;
env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
}
#endif /* !defined(__QEMU_MIPS_EXEC_H__) */

12
target-ppc/cpu.h
View File

@ -1999,4 +1999,16 @@ static inline ppcemb_tlb_t *booke206_get_tlbe(CPUState *env, const int tlbn,
extern void (*cpu_ppc_hypercall)(CPUState *);
static inline bool cpu_has_work(CPUState *env)
{
return msr_ee && (env->interrupt_request & CPU_INTERRUPT_HARD);
}
#include "exec-all.h"
static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
{
env->nip = tb->pc;
}
#endif /* !defined (__CPU_PPC_H__) */

11
target-ppc/exec.h
View File

@ -32,15 +32,4 @@ register struct CPUPPCState *env asm(AREG0);
#include "softmmu_exec.h"
#endif /* !defined(CONFIG_USER_ONLY) */
static inline bool cpu_has_work(CPUState *env)
{
return msr_ee && (env->interrupt_request & CPU_INTERRUPT_HARD);
}
static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
{
env->nip = tb->pc;
}
#endif /* !defined (__PPC_H__) */

11
target-s390x/cpu.h
View File

@ -962,4 +962,15 @@ static inline void cpu_inject_ext(CPUState *env, uint32_t code, uint32_t param,
cpu_interrupt(env, CPU_INTERRUPT_HARD);
}
static inline bool cpu_has_work(CPUState *env)
{
return (env->interrupt_request & CPU_INTERRUPT_HARD) &&
(env->psw.mask & PSW_MASK_EXT);
}
static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock* tb)
{
env->psw.addr = tb->pc;
}
#endif

12
target-s390x/exec.h
View File

@ -29,12 +29,6 @@ register struct CPUS390XState *env asm(AREG0);
#include "softmmu_exec.h"
#endif /* !defined(CONFIG_USER_ONLY) */
static inline bool cpu_has_work(CPUState *env)
{
return (env->interrupt_request & CPU_INTERRUPT_HARD) &&
(env->psw.mask & PSW_MASK_EXT);
}
static inline void regs_to_env(void)
{
}
@ -42,9 +36,3 @@ static inline void regs_to_env(void)
static inline void env_to_regs(void)
{
}
static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock* tb)
{
env->psw.addr = tb->pc;
}

13
target-sh4/cpu.h
View File

@ -361,4 +361,17 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
| (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 4 */
}
static inline bool cpu_has_work(CPUState *env)
{
return env->interrupt_request & CPU_INTERRUPT_HARD;
}
#include "exec-all.h"
static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
{
env->pc = tb->pc;
env->flags = tb->flags;
}
#endif /* _CPU_SH4_H */

11
target-sh4/exec.h
View File

@ -27,19 +27,8 @@ register struct CPUSH4State *env asm(AREG0);
#include "cpu.h"
#include "exec-all.h"
static inline bool cpu_has_work(CPUState *env)
{
return env->interrupt_request & CPU_INTERRUPT_HARD;
}
#ifndef CONFIG_USER_ONLY
#include "softmmu_exec.h"
#endif
static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
{
env->pc = tb->pc;
env->flags = tb->flags;
}
#endif /* _EXEC_SH4_H */

14
target-sparc/cpu.h
View File

@ -662,4 +662,18 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
/* helper.c */
void do_interrupt(CPUState *env);
static inline bool cpu_has_work(CPUState *env1)
{
return (env1->interrupt_request & CPU_INTERRUPT_HARD) &&
cpu_interrupts_enabled(env1);
}
#include "exec-all.h"
static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
{
env->pc = tb->pc;
env->npc = tb->cs_base;
}
#endif

14
target-sparc/exec.h
View File

@ -12,18 +12,4 @@ register struct CPUSPARCState *env asm(AREG0);
#include "softmmu_exec.h"
#endif /* !defined(CONFIG_USER_ONLY) */
/* op_helper.c */
static inline bool cpu_has_work(CPUState *env1)
{
return (env1->interrupt_request & CPU_INTERRUPT_HARD) &&
cpu_interrupts_enabled(env1);
}
static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
{
env->pc = tb->pc;
env->npc = tb->cs_base;
}
#endif

6
target-unicore32/cpu.h
View File

@ -179,4 +179,10 @@ void uc32_translate_init(void);
void do_interrupt(CPUState *);
void switch_mode(CPUState_UniCore32 *, int);
static inline bool cpu_has_work(CPUState *env)
{
return env->interrupt_request &
(CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
}
#endif /* __CPU_UC32_H__ */

6
target-unicore32/exec.h
View File

@ -26,12 +26,6 @@ static inline void regs_to_env(void)
{
}
static inline bool cpu_has_work(CPUState *env)
{
return env->interrupt_request &
(CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
}
static inline int cpu_halted(CPUState *env)
{
if (!env->halted) {

1
xen-mapcache-stub.c
View File

@ -8,6 +8,7 @@
#include "config.h"
#include "cpu.h"
#include "exec-all.h"
#include "qemu-common.h"
#include "cpu-common.h"