mirror of https://github.com/proxmox/mirror_qemu
target-arm: Add VMPIDR_EL2
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1442135278-25281-9-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>master
parent
06a7e6477c
commit
f0d574d63f
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@ -386,6 +386,7 @@ typedef struct CPUARMState {
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uint64_t c15_ccnt;
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uint64_t c15_ccnt;
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uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */
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uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */
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uint64_t vpidr_el2; /* Virtualization Processor ID Register */
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uint64_t vpidr_el2; /* Virtualization Processor ID Register */
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uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */
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} cp15;
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} cp15;
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struct {
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struct {
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@ -2477,6 +2477,12 @@ static uint64_t mpidr_read_val(CPUARMState *env)
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static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
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static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
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{
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{
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unsigned int cur_el = arm_current_el(env);
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bool secure = arm_is_secure(env);
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if (arm_feature(env, ARM_FEATURE_EL2) && !secure && cur_el == 1) {
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return env->cp15.vmpidr_el2;
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}
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return mpidr_read_val(env);
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return mpidr_read_val(env);
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}
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}
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@ -4138,6 +4144,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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define_arm_cp_regs(cpu, v8_cp_reginfo);
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define_arm_cp_regs(cpu, v8_cp_reginfo);
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}
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}
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if (arm_feature(env, ARM_FEATURE_EL2)) {
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if (arm_feature(env, ARM_FEATURE_EL2)) {
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uint64_t vmpidr_def = mpidr_read_val(env);
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ARMCPRegInfo vpidr_regs[] = {
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ARMCPRegInfo vpidr_regs[] = {
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{ .name = "VPIDR", .state = ARM_CP_STATE_AA32,
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{ .name = "VPIDR", .state = ARM_CP_STATE_AA32,
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.cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
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.cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
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@ -4148,6 +4155,16 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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.opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
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.opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
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.access = PL2_RW, .resetvalue = cpu->midr,
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.access = PL2_RW, .resetvalue = cpu->midr,
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.fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
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.fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
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{ .name = "VMPIDR", .state = ARM_CP_STATE_AA32,
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.cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
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.access = PL2_RW, .accessfn = access_el3_aa32ns,
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.resetvalue = vmpidr_def,
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.fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) },
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{ .name = "VMPIDR_EL2", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
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.access = PL2_RW,
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.resetvalue = vmpidr_def,
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.fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) },
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REGINFO_SENTINEL
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REGINFO_SENTINEL
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};
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};
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define_arm_cp_regs(cpu, vpidr_regs);
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define_arm_cp_regs(cpu, vpidr_regs);
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@ -4166,8 +4183,8 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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* register the no_el2 reginfos.
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* register the no_el2 reginfos.
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*/
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*/
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if (arm_feature(env, ARM_FEATURE_EL3)) {
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if (arm_feature(env, ARM_FEATURE_EL3)) {
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/* When EL3 exists but not EL2, VPIDR takes the value
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/* When EL3 exists but not EL2, VPIDR and VMPIDR take the value
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* of MIDR_EL1.
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* of MIDR_EL1 and MPIDR_EL1.
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*/
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*/
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ARMCPRegInfo vpidr_regs[] = {
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ARMCPRegInfo vpidr_regs[] = {
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{ .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH,
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{ .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH,
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@ -4175,6 +4192,11 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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.access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
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.access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
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.type = ARM_CP_CONST, .resetvalue = cpu->midr,
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.type = ARM_CP_CONST, .resetvalue = cpu->midr,
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.fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
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.fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
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{ .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
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.access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
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.type = ARM_CP_NO_RAW,
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.writefn = arm_cp_write_ignore, .readfn = mpidr_read },
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REGINFO_SENTINEL
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REGINFO_SENTINEL
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};
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};
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define_arm_cp_regs(cpu, vpidr_regs);
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define_arm_cp_regs(cpu, vpidr_regs);
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