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target-ppc: Bug Fix: mullwo 

On 64-bit implementations, the mullwo result is the 64 bit product of
the signed 32 bit operands.  Fix the implementation to properly deposit
the upper 32 bits into the target register.

Example:

R3 0407DED115077586
R4 53778DF3CA992E09
mullwo 3,3,4
R3 expected : FB9D02730D7735B6
R3 actual   : 000000000D7735B6 (without this patch)

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
master
Tom Musta 2014-08-12 08:45:07 -05:00 committed by Alexander Graf
parent 6ea7b35c02
commit f11ebbf8d4
1 changed files with 9 additions and 0 deletions
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9
target-ppc/translate.c
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@ -1140,11 +1140,20 @@ static void gen_mullwo(DisasContext *ctx)
{
TCGv_i32 t0 = tcg_temp_new_i32();
TCGv_i32 t1 = tcg_temp_new_i32();
#if defined(TARGET_PPC64)
TCGv_i64 t2 = tcg_temp_new_i64();
#endif
tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
tcg_gen_muls2_i32(t0, t1, t0, t1);
tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
#if defined(TARGET_PPC64)
tcg_gen_ext_i32_tl(t2, t1);
tcg_gen_deposit_i64(cpu_gpr[rD(ctx->opcode)],
cpu_gpr[rD(ctx->opcode)], t2, 32, 32);
tcg_temp_free(t2);
#endif
tcg_gen_sari_i32(t0, t0, 31);
tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);