mirror of https://github.com/proxmox/mirror_qemu
target-arm: Implement auxiliary fault status registers
Implement the auxiliary fault status registers AFSR0_EL1 and AFSR1_EL1. These are present on v7 and later, and have IMPDEF behaviour; we choose to RAZ/WI for all cores. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>master
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@ -784,6 +784,15 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
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{ .name = "AIDR", .state = ARM_CP_STATE_BOTH,
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{ .name = "AIDR", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7,
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.opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7,
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.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
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.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
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/* Auxiliary fault status registers: these also are IMPDEF, and we
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* choose to RAZ/WI for all cores.
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*/
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{ .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0,
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1,
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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/* MAIR can just read-as-written because we don't implement caches
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/* MAIR can just read-as-written because we don't implement caches
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* and so don't need to care about memory attributes.
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* and so don't need to care about memory attributes.
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*/
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*/
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