mirror of https://github.com/proxmox/mirror_qemu
target/riscv: Reassign instructions to the Zbs-extension
The following instructions are part of Zbs: - b{set,clr,ext,inv} - b{set,clr,ext,inv}i Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Acked-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20210911140016.834071-9-philipp.tomsich@vrull.eu Signed-off-by: Alistair Francis <alistair.francis@wdc.com>master
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@ -689,19 +689,11 @@ min 0000101 .......... 100 ..... 0110011 @r
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minu 0000101 .......... 101 ..... 0110011 @r
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max 0000101 .......... 110 ..... 0110011 @r
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maxu 0000101 .......... 111 ..... 0110011 @r
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bset 0010100 .......... 001 ..... 0110011 @r
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bclr 0100100 .......... 001 ..... 0110011 @r
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binv 0110100 .......... 001 ..... 0110011 @r
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bext 0100100 .......... 101 ..... 0110011 @r
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ror 0110000 .......... 101 ..... 0110011 @r
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rol 0110000 .......... 001 ..... 0110011 @r
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grev 0110100 .......... 101 ..... 0110011 @r
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gorc 0010100 .......... 101 ..... 0110011 @r
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bseti 00101. ........... 001 ..... 0010011 @sh
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bclri 01001. ........... 001 ..... 0010011 @sh
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binvi 01101. ........... 001 ..... 0010011 @sh
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bexti 01001. ........... 101 ..... 0010011 @sh
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rori 01100. ........... 101 ..... 0010011 @sh
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grevi 01101. ........... 101 ..... 0010011 @sh
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gorci 00101. ........... 101 ..... 0010011 @sh
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@ -722,3 +714,12 @@ roriw 0110000 .......... 101 ..... 0011011 @sh5
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greviw 0110100 .......... 101 ..... 0011011 @sh5
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gorciw 0010100 .......... 101 ..... 0011011 @sh5
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# *** RV32 Zbs Standard Extension ***
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bclr 0100100 .......... 001 ..... 0110011 @r
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bclri 01001. ........... 001 ..... 0010011 @sh
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bext 0100100 .......... 101 ..... 0110011 @r
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bexti 01001. ........... 101 ..... 0010011 @sh
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binv 0110100 .......... 001 ..... 0110011 @r
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binvi 01101. ........... 001 ..... 0010011 @sh
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bset 0010100 .......... 001 ..... 0110011 @r
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bseti 00101. ........... 001 ..... 0010011 @sh
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@ -1,5 +1,5 @@
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/*
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* RISC-V translation routines for the RVB draft and Zba Standard Extension.
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* RISC-V translation routines for the RVB draft Zb[as] Standard Extension.
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*
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* Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
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* Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
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@ -24,11 +24,16 @@
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} \
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} while (0)
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#define REQUIRE_ZBS(ctx) do { \
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if (!RISCV_CPU(ctx->cs)->cfg.ext_zbs) { \
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return false; \
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} \
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} while (0)
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static void gen_clz(TCGv ret, TCGv arg1)
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{
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tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
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}
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static bool trans_clz(DisasContext *ctx, arg_clz *a)
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{
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REQUIRE_EXT(ctx, RVB);
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@ -165,13 +170,13 @@ static void gen_bset(TCGv ret, TCGv arg1, TCGv shamt)
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static bool trans_bset(DisasContext *ctx, arg_bset *a)
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{
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REQUIRE_EXT(ctx, RVB);
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REQUIRE_ZBS(ctx);
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return gen_shift(ctx, a, EXT_NONE, gen_bset);
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}
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static bool trans_bseti(DisasContext *ctx, arg_bseti *a)
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{
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REQUIRE_EXT(ctx, RVB);
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REQUIRE_ZBS(ctx);
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return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bset);
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}
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@ -187,13 +192,13 @@ static void gen_bclr(TCGv ret, TCGv arg1, TCGv shamt)
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static bool trans_bclr(DisasContext *ctx, arg_bclr *a)
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{
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REQUIRE_EXT(ctx, RVB);
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REQUIRE_ZBS(ctx);
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return gen_shift(ctx, a, EXT_NONE, gen_bclr);
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}
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static bool trans_bclri(DisasContext *ctx, arg_bclri *a)
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{
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REQUIRE_EXT(ctx, RVB);
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REQUIRE_ZBS(ctx);
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return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bclr);
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}
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@ -209,13 +214,13 @@ static void gen_binv(TCGv ret, TCGv arg1, TCGv shamt)
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static bool trans_binv(DisasContext *ctx, arg_binv *a)
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{
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REQUIRE_EXT(ctx, RVB);
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REQUIRE_ZBS(ctx);
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return gen_shift(ctx, a, EXT_NONE, gen_binv);
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}
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static bool trans_binvi(DisasContext *ctx, arg_binvi *a)
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{
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REQUIRE_EXT(ctx, RVB);
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REQUIRE_ZBS(ctx);
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return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_binv);
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}
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@ -227,13 +232,13 @@ static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt)
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static bool trans_bext(DisasContext *ctx, arg_bext *a)
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{
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REQUIRE_EXT(ctx, RVB);
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REQUIRE_ZBS(ctx);
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return gen_shift(ctx, a, EXT_NONE, gen_bext);
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}
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static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
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{
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REQUIRE_EXT(ctx, RVB);
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REQUIRE_ZBS(ctx);
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return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bext);
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}
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