mirror of https://github.com/proxmox/mirror_qemu
tcg: Add host memory barriers to cpu_ldst.h interfaces
Bring the helpers into line with the rest of tcg in respecting guest memory ordering. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>master
Richard Henderson
parent
c914d46d0a
commit
f86e8f3d13
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@ -2339,6 +2339,7 @@ static uint8_t do_ld1_mmu(CPUArchState *env, vaddr addr, MemOpIdx oi,
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MMULookupLocals l;
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bool crosspage;
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cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);
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crosspage = mmu_lookup(env, addr, oi, ra, access_type, &l);
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tcg_debug_assert(!crosspage);
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@ -2360,6 +2361,7 @@ static uint16_t do_ld2_mmu(CPUArchState *env, vaddr addr, MemOpIdx oi,
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uint16_t ret;
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uint8_t a, b;
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cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);
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crosspage = mmu_lookup(env, addr, oi, ra, access_type, &l);
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if (likely(!crosspage)) {
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return do_ld_2(env, &l.page[0], l.mmu_idx, access_type, l.memop, ra);
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@ -2390,6 +2392,7 @@ static uint32_t do_ld4_mmu(CPUArchState *env, vaddr addr, MemOpIdx oi,
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bool crosspage;
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uint32_t ret;
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cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);
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crosspage = mmu_lookup(env, addr, oi, ra, access_type, &l);
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if (likely(!crosspage)) {
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return do_ld_4(env, &l.page[0], l.mmu_idx, access_type, l.memop, ra);
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@ -2417,6 +2420,7 @@ static uint64_t do_ld8_mmu(CPUArchState *env, vaddr addr, MemOpIdx oi,
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bool crosspage;
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uint64_t ret;
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cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);
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crosspage = mmu_lookup(env, addr, oi, ra, access_type, &l);
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if (likely(!crosspage)) {
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return do_ld_8(env, &l.page[0], l.mmu_idx, access_type, l.memop, ra);
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@ -2469,6 +2473,7 @@ static Int128 do_ld16_mmu(CPUArchState *env, vaddr addr,
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Int128 ret;
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int first;
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cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);
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crosspage = mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD, &l);
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if (likely(!crosspage)) {
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/* Perform the load host endian. */
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@ -2802,6 +2807,7 @@ void helper_stb_mmu(CPUArchState *env, uint64_t addr, uint32_t val,
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bool crosspage;
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tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_8);
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cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST);
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crosspage = mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE, &l);
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tcg_debug_assert(!crosspage);
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@ -2815,6 +2821,7 @@ static void do_st2_mmu(CPUArchState *env, vaddr addr, uint16_t val,
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bool crosspage;
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uint8_t a, b;
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cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST);
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crosspage = mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE, &l);
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if (likely(!crosspage)) {
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do_st_2(env, &l.page[0], val, l.mmu_idx, l.memop, ra);
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@ -2843,6 +2850,7 @@ static void do_st4_mmu(CPUArchState *env, vaddr addr, uint32_t val,
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MMULookupLocals l;
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bool crosspage;
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cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST);
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crosspage = mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE, &l);
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if (likely(!crosspage)) {
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do_st_4(env, &l.page[0], val, l.mmu_idx, l.memop, ra);
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@ -2870,6 +2878,7 @@ static void do_st8_mmu(CPUArchState *env, vaddr addr, uint64_t val,
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MMULookupLocals l;
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bool crosspage;
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cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST);
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crosspage = mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE, &l);
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if (likely(!crosspage)) {
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do_st_8(env, &l.page[0], val, l.mmu_idx, l.memop, ra);
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@ -2899,6 +2908,7 @@ static void do_st16_mmu(CPUArchState *env, vaddr addr, Int128 val,
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uint64_t a, b;
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int first;
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cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST);
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crosspage = mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE, &l);
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if (likely(!crosspage)) {
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/* Swap to host endian if necessary, then store. */
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@ -78,4 +78,38 @@ extern int64_t max_advance;
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extern bool one_insn_per_tb;
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/**
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* tcg_req_mo:
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* @type: TCGBar
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*
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* Filter @type to the barrier that is required for the guest
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* memory ordering vs the host memory ordering. A non-zero
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* result indicates that some barrier is required.
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*
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* If TCG_GUEST_DEFAULT_MO is not defined, assume that the
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* guest requires strict ordering.
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*
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* This is a macro so that it's constant even without optimization.
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*/
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#ifdef TCG_GUEST_DEFAULT_MO
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# define tcg_req_mo(type) \
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((type) & TCG_GUEST_DEFAULT_MO & ~TCG_TARGET_DEFAULT_MO)
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#else
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# define tcg_req_mo(type) ((type) & ~TCG_TARGET_DEFAULT_MO)
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#endif
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/**
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* cpu_req_mo:
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* @type: TCGBar
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*
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* If tcg_req_mo indicates a barrier for @type is required
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* for the guest memory model, issue a host memory barrier.
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*/
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#define cpu_req_mo(type) \
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do { \
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if (tcg_req_mo(type)) { \
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smp_mb(); \
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} \
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} while (0)
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#endif /* ACCEL_TCG_INTERNAL_H */
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@ -914,6 +914,7 @@ static uint8_t do_ld1_mmu(CPUArchState *env, abi_ptr addr,
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uint8_t ret;
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tcg_debug_assert((mop & MO_SIZE) == MO_8);
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cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);
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haddr = cpu_mmu_lookup(env, addr, mop, ra, MMU_DATA_LOAD);
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ret = ldub_p(haddr);
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clear_helper_retaddr();
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@ -947,6 +948,7 @@ static uint16_t do_ld2_mmu(CPUArchState *env, abi_ptr addr,
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uint16_t ret;
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tcg_debug_assert((mop & MO_SIZE) == MO_16);
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cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);
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haddr = cpu_mmu_lookup(env, addr, mop, ra, MMU_DATA_LOAD);
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ret = load_atom_2(env, ra, haddr, mop);
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clear_helper_retaddr();
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@ -984,6 +986,7 @@ static uint32_t do_ld4_mmu(CPUArchState *env, abi_ptr addr,
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uint32_t ret;
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tcg_debug_assert((mop & MO_SIZE) == MO_32);
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cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);
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haddr = cpu_mmu_lookup(env, addr, mop, ra, MMU_DATA_LOAD);
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ret = load_atom_4(env, ra, haddr, mop);
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clear_helper_retaddr();
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@ -1021,6 +1024,7 @@ static uint64_t do_ld8_mmu(CPUArchState *env, abi_ptr addr,
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uint64_t ret;
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tcg_debug_assert((mop & MO_SIZE) == MO_64);
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cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);
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haddr = cpu_mmu_lookup(env, addr, mop, ra, MMU_DATA_LOAD);
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ret = load_atom_8(env, ra, haddr, mop);
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clear_helper_retaddr();
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@ -1052,6 +1056,7 @@ static Int128 do_ld16_mmu(CPUArchState *env, abi_ptr addr,
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Int128 ret;
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tcg_debug_assert((mop & MO_SIZE) == MO_128);
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cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);
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haddr = cpu_mmu_lookup(env, addr, mop, ra, MMU_DATA_LOAD);
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ret = load_atom_16(env, ra, haddr, mop);
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clear_helper_retaddr();
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@ -1087,6 +1092,7 @@ static void do_st1_mmu(CPUArchState *env, abi_ptr addr, uint8_t val,
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void *haddr;
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tcg_debug_assert((mop & MO_SIZE) == MO_8);
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cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST);
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haddr = cpu_mmu_lookup(env, addr, mop, ra, MMU_DATA_STORE);
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stb_p(haddr, val);
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clear_helper_retaddr();
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@ -1111,6 +1117,7 @@ static void do_st2_mmu(CPUArchState *env, abi_ptr addr, uint16_t val,
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void *haddr;
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tcg_debug_assert((mop & MO_SIZE) == MO_16);
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cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST);
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haddr = cpu_mmu_lookup(env, addr, mop, ra, MMU_DATA_STORE);
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if (mop & MO_BSWAP) {
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@ -1139,6 +1146,7 @@ static void do_st4_mmu(CPUArchState *env, abi_ptr addr, uint32_t val,
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void *haddr;
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tcg_debug_assert((mop & MO_SIZE) == MO_32);
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cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST);
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haddr = cpu_mmu_lookup(env, addr, mop, ra, MMU_DATA_STORE);
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if (mop & MO_BSWAP) {
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@ -1167,6 +1175,7 @@ static void do_st8_mmu(CPUArchState *env, abi_ptr addr, uint64_t val,
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void *haddr;
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tcg_debug_assert((mop & MO_SIZE) == MO_64);
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cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST);
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haddr = cpu_mmu_lookup(env, addr, mop, ra, MMU_DATA_STORE);
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if (mop & MO_BSWAP) {
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@ -1195,6 +1204,7 @@ static void do_st16_mmu(CPUArchState *env, abi_ptr addr, Int128 val,
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void *haddr;
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tcg_debug_assert((mop & MO_SIZE) == MO_128);
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cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST);
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haddr = cpu_mmu_lookup(env, addr, mop, ra, MMU_DATA_STORE);
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if (mop & MO_BSWAP) {
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