mirror of https://github.com/proxmox/mirror_qemu
target/arm: Convert the VFP load/store multiple insns to decodetree
Convert the VFP load/store multiple insns to decodetree. This includes tightening up the UNDEF checking for pre-VFPv3 CPUs which only have D0-D15 : they now UNDEF for any access to D16-D31, not merely when the smallest register in the transfer list is in D16-D31. This conversion does not try to share code between the single precision and the double precision versions; this looks a bit duplicative of code, but it leaves the door open for a future refactoring which gets rid of the use of the "F0" registers by inlining the various functions like gen_vfp_ld() and gen_mov_F0_reg() which are hiding "if (dp) { ... } else { ... }" conditionalisation. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>master
parent
79b02a3b52
commit
fa288de272
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@ -926,3 +926,165 @@ static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_VLDR_VSTR_sp *a)
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return true;
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}
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static bool trans_VLDM_VSTM_sp(DisasContext *s, arg_VLDM_VSTM_sp *a)
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{
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uint32_t offset;
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TCGv_i32 addr;
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int i, n;
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n = a->imm;
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if (n == 0 || (a->vd + n) > 32) {
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/*
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* UNPREDICTABLE cases for bad immediates: we choose to
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* UNDEF to avoid generating huge numbers of TCG ops
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*/
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return false;
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}
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if (a->rn == 15 && a->w) {
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/* writeback to PC is UNPREDICTABLE, we choose to UNDEF */
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return false;
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}
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if (!vfp_access_check(s)) {
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return true;
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}
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if (s->thumb && a->rn == 15) {
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/* This is actually UNPREDICTABLE */
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addr = tcg_temp_new_i32();
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tcg_gen_movi_i32(addr, s->pc & ~2);
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} else {
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addr = load_reg(s, a->rn);
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}
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if (a->p) {
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/* pre-decrement */
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tcg_gen_addi_i32(addr, addr, -(a->imm << 2));
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}
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if (s->v8m_stackcheck && a->rn == 13 && a->w) {
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/*
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* Here 'addr' is the lowest address we will store to,
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* and is either the old SP (if post-increment) or
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* the new SP (if pre-decrement). For post-increment
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* where the old value is below the limit and the new
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* value is above, it is UNKNOWN whether the limit check
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* triggers; we choose to trigger.
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*/
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gen_helper_v8m_stackcheck(cpu_env, addr);
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}
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offset = 4;
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for (i = 0; i < n; i++) {
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if (a->l) {
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/* load */
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gen_vfp_ld(s, false, addr);
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gen_mov_vreg_F0(false, a->vd + i);
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} else {
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/* store */
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gen_mov_F0_vreg(false, a->vd + i);
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gen_vfp_st(s, false, addr);
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}
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tcg_gen_addi_i32(addr, addr, offset);
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}
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if (a->w) {
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/* writeback */
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if (a->p) {
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offset = -offset * n;
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tcg_gen_addi_i32(addr, addr, offset);
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}
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store_reg(s, a->rn, addr);
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} else {
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tcg_temp_free_i32(addr);
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}
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return true;
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}
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static bool trans_VLDM_VSTM_dp(DisasContext *s, arg_VLDM_VSTM_dp *a)
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{
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uint32_t offset;
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TCGv_i32 addr;
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int i, n;
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n = a->imm >> 1;
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if (n == 0 || (a->vd + n) > 32 || n > 16) {
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/*
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* UNPREDICTABLE cases for bad immediates: we choose to
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* UNDEF to avoid generating huge numbers of TCG ops
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*/
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return false;
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}
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if (a->rn == 15 && a->w) {
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/* writeback to PC is UNPREDICTABLE, we choose to UNDEF */
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return false;
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}
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/* UNDEF accesses to D16-D31 if they don't exist */
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if (!dc_isar_feature(aa32_fp_d32, s) && (a->vd + n) > 16) {
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return false;
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}
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if (!vfp_access_check(s)) {
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return true;
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}
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if (s->thumb && a->rn == 15) {
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/* This is actually UNPREDICTABLE */
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addr = tcg_temp_new_i32();
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tcg_gen_movi_i32(addr, s->pc & ~2);
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} else {
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addr = load_reg(s, a->rn);
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}
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if (a->p) {
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/* pre-decrement */
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tcg_gen_addi_i32(addr, addr, -(a->imm << 2));
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}
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if (s->v8m_stackcheck && a->rn == 13 && a->w) {
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/*
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* Here 'addr' is the lowest address we will store to,
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* and is either the old SP (if post-increment) or
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* the new SP (if pre-decrement). For post-increment
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* where the old value is below the limit and the new
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* value is above, it is UNKNOWN whether the limit check
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* triggers; we choose to trigger.
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*/
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gen_helper_v8m_stackcheck(cpu_env, addr);
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}
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offset = 8;
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for (i = 0; i < n; i++) {
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if (a->l) {
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/* load */
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gen_vfp_ld(s, true, addr);
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gen_mov_vreg_F0(true, a->vd + i);
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} else {
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/* store */
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gen_mov_F0_vreg(true, a->vd + i);
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gen_vfp_st(s, true, addr);
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}
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tcg_gen_addi_i32(addr, addr, offset);
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}
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if (a->w) {
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/* writeback */
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if (a->p) {
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offset = -offset * n;
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} else if (a->imm & 1) {
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offset = 4;
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} else {
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offset = 0;
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}
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if (offset != 0) {
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tcg_gen_addi_i32(addr, addr, offset);
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}
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store_reg(s, a->rn, addr);
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} else {
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tcg_temp_free_i32(addr);
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}
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return true;
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}
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@ -3092,9 +3092,8 @@ static void gen_neon_dup_high16(TCGv_i32 var)
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*/
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static int disas_vfp_insn(DisasContext *s, uint32_t insn)
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{
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uint32_t rd, rn, rm, op, i, n, offset, delta_d, delta_m, bank_mask;
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uint32_t rd, rn, rm, op, i, n, delta_d, delta_m, bank_mask;
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int dp, veclen;
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TCGv_i32 addr;
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TCGv_i32 tmp;
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TCGv_i32 tmp2;
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@ -3702,98 +3701,8 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
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break;
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case 0xc:
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case 0xd:
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if ((insn & 0x03e00000) == 0x00400000) {
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/* Already handled by decodetree */
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return 1;
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} else {
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/* Load/store */
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rn = (insn >> 16) & 0xf;
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if (dp)
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VFP_DREG_D(rd, insn);
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else
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rd = VFP_SREG_D(insn);
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if ((insn & 0x01200000) == 0x01000000) {
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/* Already handled by decodetree */
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return 1;
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} else {
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/* load/store multiple */
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int w = insn & (1 << 21);
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if (dp)
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n = (insn >> 1) & 0x7f;
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else
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n = insn & 0xff;
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if (w && !(((insn >> 23) ^ (insn >> 24)) & 1)) {
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/* P == U , W == 1 => UNDEF */
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return 1;
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}
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if (n == 0 || (rd + n) > 32 || (dp && n > 16)) {
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/* UNPREDICTABLE cases for bad immediates: we choose to
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* UNDEF to avoid generating huge numbers of TCG ops
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*/
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return 1;
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}
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if (rn == 15 && w) {
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/* writeback to PC is UNPREDICTABLE, we choose to UNDEF */
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return 1;
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}
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if (s->thumb && rn == 15) {
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/* This is actually UNPREDICTABLE */
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addr = tcg_temp_new_i32();
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tcg_gen_movi_i32(addr, s->pc & ~2);
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} else {
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addr = load_reg(s, rn);
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}
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if (insn & (1 << 24)) /* pre-decrement */
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tcg_gen_addi_i32(addr, addr, -((insn & 0xff) << 2));
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if (s->v8m_stackcheck && rn == 13 && w) {
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/*
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* Here 'addr' is the lowest address we will store to,
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* and is either the old SP (if post-increment) or
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* the new SP (if pre-decrement). For post-increment
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* where the old value is below the limit and the new
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* value is above, it is UNKNOWN whether the limit check
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* triggers; we choose to trigger.
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*/
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gen_helper_v8m_stackcheck(cpu_env, addr);
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}
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if (dp)
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offset = 8;
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else
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offset = 4;
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for (i = 0; i < n; i++) {
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if (insn & ARM_CP_RW_BIT) {
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/* load */
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gen_vfp_ld(s, dp, addr);
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gen_mov_vreg_F0(dp, rd + i);
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} else {
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/* store */
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gen_mov_F0_vreg(dp, rd + i);
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gen_vfp_st(s, dp, addr);
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}
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tcg_gen_addi_i32(addr, addr, offset);
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}
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if (w) {
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/* writeback */
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if (insn & (1 << 24))
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offset = -offset * n;
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else if (dp && (insn & 1))
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offset = 4;
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else
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offset = 0;
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if (offset != 0)
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tcg_gen_addi_i32(addr, addr, offset);
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store_reg(s, rn, addr);
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} else {
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tcg_temp_free_i32(addr);
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}
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}
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}
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break;
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/* Already handled by decodetree */
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return 1;
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default:
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/* Should never happen. */
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return 1;
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@ -78,3 +78,21 @@ VLDR_VSTR_sp ---- 1101 u:1 .0 l:1 rn:4 .... 1010 imm:8 \
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vd=%vd_sp
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VLDR_VSTR_dp ---- 1101 u:1 .0 l:1 rn:4 .... 1011 imm:8 \
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vd=%vd_dp
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# We split the load/store multiple up into two patterns to avoid
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# overlap with other insns in the "Advanced SIMD load/store and 64-bit move"
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# grouping:
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# P=0 U=0 W=0 is 64-bit VMOV
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# P=1 W=0 is VLDR/VSTR
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# P=U W=1 is UNDEF
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# leaving P=0 U=1 W=x and P=1 U=0 W=1 for load/store multiple.
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# These include FSTM/FLDM.
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VLDM_VSTM_sp ---- 1100 1 . w:1 l:1 rn:4 .... 1010 imm:8 \
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vd=%vd_sp p=0 u=1
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VLDM_VSTM_dp ---- 1100 1 . w:1 l:1 rn:4 .... 1011 imm:8 \
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vd=%vd_dp p=0 u=1
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VLDM_VSTM_sp ---- 1101 0.1 l:1 rn:4 .... 1010 imm:8 \
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vd=%vd_sp p=1 u=0 w=1
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VLDM_VSTM_dp ---- 1101 0.1 l:1 rn:4 .... 1011 imm:8 \
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vd=%vd_dp p=1 u=0 w=1
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