mirror of https://github.com/proxmox/mirror_qemu
OpenRISC updates for 7.2.0
Updates to add the OpenRISC virt plaform to QEMU. Highlights include: - New virt plaform with, virtio and pci bus support - OpenRISC support for MTTCG - Goldfish RTC device endianness is configurable now -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEE2cRzVK74bBA6Je/xw7McLV5mJ+QFAmMURl4ACgkQw7McLV5m J+TAVg/6A1HFazEBDzyVvg5BWfusvPMv1gWyAXQVbZDdoEVP5ilJq3Xz2vlOWu+Q 46WHAncQH8KGWlS7x4Qk9X1tOU+9LCTa0aBqa1ARAle/wGKJeQ2QkmQM7lnAAtFt ON9pDOrj85cNVp7ly/rZqmOkYorUtSblKllOigPaxZozfSA2FuoYwc7vLxy/ICk0 6RbRUKiIvqvNxhT0q13buIiqhtQAOLC2/Rrlp/CqUm+nrNlSVQIMC57ddNoopUFN I6jb5UxyHtQSlWX6zsLjvho9hlZCuA9IIG7B4qS4/kyC7XJGmOICb3A7QSmfaUxy HtEsaImjjhCUnJs8fhDHqyYnUu6JcXMRv61hIr7GNK/g3enpBzG1Otu5jsyHgzEX SaachdFUibLJSj/+K4YOaT9luAc0Yvx9vArnXD+2wGg3kHTSDUNv2nFdyLyn5PNM sZ9gx6gTEFI7iaeHEZM/doKdlHubddA/GH4DLy2fwZN7EyIsbll9TDJ8icqu1UBT KpQdN55VeVqdOEvKUSXxsAK8aRtTjlEErKinufz1yyrg5Lw9XgH1xtTft+rJyXPu Lw0hMHYqeaWhNUgnli/ByTY7yd+wC/ukNFQLUlMiDte337Lx9H//MOVvyl6Y5ARE jIWt1JlTyuhj+txJrGZMvBrc2ZQ6fF/4HXc/xyGK7eJnEWZIzkY= =BzgX -----END PGP SIGNATURE----- Merge tag 'pull-or1k-20220904' of https://github.com/stffrdhrn/qemu into staging OpenRISC updates for 7.2.0 Updates to add the OpenRISC virt plaform to QEMU. Highlights include: - New virt plaform with, virtio and pci bus support - OpenRISC support for MTTCG - Goldfish RTC device endianness is configurable now # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE2cRzVK74bBA6Je/xw7McLV5mJ+QFAmMURl4ACgkQw7McLV5m # J+TAVg/6A1HFazEBDzyVvg5BWfusvPMv1gWyAXQVbZDdoEVP5ilJq3Xz2vlOWu+Q # 46WHAncQH8KGWlS7x4Qk9X1tOU+9LCTa0aBqa1ARAle/wGKJeQ2QkmQM7lnAAtFt # ON9pDOrj85cNVp7ly/rZqmOkYorUtSblKllOigPaxZozfSA2FuoYwc7vLxy/ICk0 # 6RbRUKiIvqvNxhT0q13buIiqhtQAOLC2/Rrlp/CqUm+nrNlSVQIMC57ddNoopUFN # I6jb5UxyHtQSlWX6zsLjvho9hlZCuA9IIG7B4qS4/kyC7XJGmOICb3A7QSmfaUxy # HtEsaImjjhCUnJs8fhDHqyYnUu6JcXMRv61hIr7GNK/g3enpBzG1Otu5jsyHgzEX # SaachdFUibLJSj/+K4YOaT9luAc0Yvx9vArnXD+2wGg3kHTSDUNv2nFdyLyn5PNM # sZ9gx6gTEFI7iaeHEZM/doKdlHubddA/GH4DLy2fwZN7EyIsbll9TDJ8icqu1UBT # KpQdN55VeVqdOEvKUSXxsAK8aRtTjlEErKinufz1yyrg5Lw9XgH1xtTft+rJyXPu # Lw0hMHYqeaWhNUgnli/ByTY7yd+wC/ukNFQLUlMiDte337Lx9H//MOVvyl6Y5ARE # jIWt1JlTyuhj+txJrGZMvBrc2ZQ6fF/4HXc/xyGK7eJnEWZIzkY= # =BzgX # -----END PGP SIGNATURE----- # gpg: Signature made Sun 04 Sep 2022 02:31:58 EDT # gpg: using RSA key D9C47354AEF86C103A25EFF1C3B31C2D5E6627E4 # gpg: Good signature from "Stafford Horne <shorne@gmail.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: D9C4 7354 AEF8 6C10 3A25 EFF1 C3B3 1C2D 5E66 27E4 * tag 'pull-or1k-20220904' of https://github.com/stffrdhrn/qemu: docs/system: openrisc: Add OpenRISC documentation hw/openrisc: virt: pass random seed to fdt target/openrisc: Interrupt handling fixes target/openrisc: Enable MTTCG target/openrisc: Add interrupted CPU to log hw/openrisc: Initialize timer time at startup hw/openrisc: Add PCI bus support to virt hw/openrisc: Add the OpenRISC virtual machine goldfish_rtc: Add big-endian property target/openrisc: Fix memory reading in debugger hw/openrisc: Split re-usable boot time apis out to boot.c Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>master
Stefan Hajnoczi
commit
fd28528ece
|
|
@ -3,3 +3,4 @@
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# Boards:
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#
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CONFIG_OR1K_SIM=y
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CONFIG_OR1K_VIRT=y
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|
|
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@ -1,3 +1,4 @@
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TARGET_ARCH=openrisc
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TARGET_SUPPORTS_MTTCG=y
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TARGET_BIG_ENDIAN=y
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TARGET_NEED_FDT=y
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|
|
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|
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@ -0,0 +1,15 @@
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CPU Features
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============
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The QEMU emulation of the OpenRISC architecture provides following built in
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features.
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- Shadow GPRs
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- MMU TLB with 128 entries, 1 way
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- Power Management (PM)
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- Programmable Interrupt Controller (PIC)
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- Tick Timer
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These features are on by default and the presence can be confirmed by checking
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the contents of the Unit Presence Register (``UPR``) and CPU Configuration
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Register (``CPUCFGR``).
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@ -0,0 +1,17 @@
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OpenRISC 1000 CPU architecture support
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======================================
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QEMU's TCG emulation includes support for the OpenRISC or1200 implementation of
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the OpenRISC 1000 cpu architecture.
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The or1200 cpu also has support for the following instruction subsets:
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- ORBIS32 (OpenRISC Basic Instruction Set)
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- ORFPX32 (OpenRISC Floating-Point eXtension)
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In addition to the instruction subsets the QEMU TCG emulation also has support
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for most Class II (optional) instructions.
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For information on all OpenRISC instructions please refer to the latest
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architecture manual available on the OpenRISC website in the
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`OpenRISC Architecture <https://openrisc.io/architecture>`_ section.
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@ -0,0 +1,43 @@
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Or1ksim board
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=============
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The QEMU Or1ksim machine emulates the standard OpenRISC board simulator which is
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also the standard SoC configuration.
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Supported devices
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-----------------
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* 16550A UART
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* ETHOC Ethernet controller
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* SMP (OpenRISC multicore using ompic)
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Boot options
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------------
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The Or1ksim machine can be started using the ``-kernel`` and ``-initrd`` options
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to load a Linux kernel and optional disk image.
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.. code-block:: bash
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$ qemu-system-or1k -cpu or1220 -M or1k-sim -nographic \
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-kernel vmlinux \
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-initrd initramfs.cpio.gz \
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-m 128
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Linux guest kernel configuration
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""""""""""""""""""""""""""""""""
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The 'or1ksim_defconfig' for Linux openrisc kernels includes the right
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drivers for the or1ksim machine. If you would like to run an SMP system
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choose the 'simple_smp_defconfig' config.
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Hardware configuration information
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""""""""""""""""""""""""""""""""""
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The ``or1k-sim`` board automatically generates a device tree blob ("dtb")
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which it passes to the guest. This provides information about the
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addresses, interrupt lines and other configuration of the various devices
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in the system.
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The location of the DTB will be passed in register ``r3`` to the guest operating
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system.
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@ -0,0 +1,50 @@
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'virt' generic virtual platform
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===============================
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The ``virt`` board is a platform which does not correspond to any
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real hardware; it is designed for use in virtual machines.
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It is the recommended board type if you simply want to run
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a guest such as Linux and do not care about reproducing the
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idiosyncrasies and limitations of a particular bit of real-world
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hardware.
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Supported devices
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-----------------
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* PCI/PCIe devices
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* 8 virtio-mmio transport devices
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* 16550A UART
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* Goldfish RTC
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* SiFive Test device for poweroff and reboot
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* SMP (OpenRISC multicore using ompic)
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Boot options
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------------
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The virt machine can be started using the ``-kernel`` and ``-initrd`` options
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to load a Linux kernel and optional disk image. For example:
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.. code-block:: bash
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$ qemu-system-or1k -cpu or1220 -M or1k-sim -nographic \
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-device virtio-net-device,netdev=user -netdev user,id=user,net=10.9.0.1/24,host=10.9.0.100 \
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-device virtio-blk-device,drive=d0 -drive file=virt.qcow2,id=d0,if=none,format=qcow2 \
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-kernel vmlinux \
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-initrd initramfs.cpio.gz \
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-m 128
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Linux guest kernel configuration
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""""""""""""""""""""""""""""""""
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|
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The 'virt_defconfig' for Linux openrisc kernels includes the right drivers for
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the ``virt`` machine.
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|
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Hardware configuration information
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||||
""""""""""""""""""""""""""""""""""
|
||||
|
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The ``virt`` board automatically generates a device tree blob ("dtb") which it
|
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passes to the guest. This provides information about the addresses, interrupt
|
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lines and other configuration of the various devices in the system.
|
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|
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The location of the DTB will be passed in register ``r3`` to the guest operating
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system.
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|
|
@ -0,0 +1,71 @@
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|||
.. _OpenRISC-System-emulator:
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OpenRISC System emulator
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~~~~~~~~~~~~~~~~~~~~~~~~
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QEMU can emulate 32-bit OpenRISC CPUs using the ``qemu-system-or1k`` executable.
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OpenRISC CPUs are generally built into "system-on-chip" (SoC) designs that run
|
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on FPGAs. These SoCs are based on the same core architecture as the or1ksim
|
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(the original OpenRISC instruction level simulator) which QEMU supports. For
|
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this reason QEMU does not need to support many different boards to support the
|
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OpenRISC hardware ecosystem.
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The OpenRISC CPU supported by QEMU is the ``or1200``, it supports an MMU and can
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run linux.
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Choosing a board model
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======================
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For QEMU's OpenRISC system emulation, you must specify which board model you
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want to use with the ``-M`` or ``--machine`` option; the default machine is
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``or1k-sim``.
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If you intend to boot Linux, it is possible to have a single kernel image that
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will boot on any of the QEMU machines. To do this one would compile all required
|
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drivers into the kernel. This is possible because QEMU will create a device tree
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structure that describes the QEMU machine and pass a pointer to the structure to
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the kernel. The kernel can then use this to configure itself for the machine.
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|
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However, typically users will have specific firmware images for a specific machine.
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If you already have a system image or a kernel that works on hardware and you
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want to boot with QEMU, check whether QEMU lists that machine in its ``-machine
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help`` output. If it is listed, then you can probably use that board model. If
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it is not listed, then unfortunately your image will almost certainly not boot
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on QEMU. (You might be able to extract the filesystem and use that with a
|
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different kernel which boots on a system that QEMU does emulate.)
|
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|
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If you don't care about reproducing the idiosyncrasies of a particular
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bit of hardware, such as small amount of RAM, no PCI or other hard disk, etc.,
|
||||
and just want to run Linux, the best option is to use the ``virt`` board. This
|
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is a platform which doesn't correspond to any real hardware and is designed for
|
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use in virtual machines. You'll need to compile Linux with a suitable
|
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configuration for running on the ``virt`` board. ``virt`` supports PCI, virtio
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and large amounts of RAM.
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Board-specific documentation
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||||
============================
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||||
..
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This table of contents should be kept sorted alphabetically
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by the title text of each file, which isn't the same ordering
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as an alphabetical sort by filename.
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.. toctree::
|
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:maxdepth: 1
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|
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openrisc/or1k-sim
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openrisc/virt
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Emulated CPU architecture support
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||||
=================================
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.. toctree::
|
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openrisc/emulation
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OpenRISC CPU features
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=====================
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.. toctree::
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openrisc/cpu-features
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|
@ -21,6 +21,7 @@ Contents:
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|||
target-m68k
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target-mips
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target-ppc
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target-openrisc
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target-riscv
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target-rx
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target-s390x
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|
|
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@ -173,6 +173,7 @@ static void virt_init(MachineState *machine)
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io_base = VIRT_GF_RTC_MMIO_BASE;
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for (i = 0; i < VIRT_GF_RTC_NB; i++) {
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dev = qdev_new(TYPE_GOLDFISH_RTC);
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qdev_prop_set_bit(dev, "big-endian", true);
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sysbus = SYS_BUS_DEVICE(dev);
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sysbus_realize_and_unref(sysbus, &error_fatal);
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sysbus_mmio_map(sysbus, 0, io_base);
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|
|
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@ -4,3 +4,15 @@ config OR1K_SIM
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select OPENCORES_ETH
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select OMPIC
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select SPLIT_IRQ
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config OR1K_VIRT
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bool
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imply PCI_DEVICES
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imply VIRTIO_VGA
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imply TEST_DEVICES
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select PCI
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select PCI_EXPRESS_GENERIC_BRIDGE
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select GOLDFISH_RTC
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select SERIAL
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select SIFIVE_TEST
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select VIRTIO_MMIO
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|
|
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|||
|
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@ -0,0 +1,116 @@
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/*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*
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* QEMU OpenRISC boot helpers.
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*
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* (c) 2022 Stafford Horne <shorne@gmail.com>
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/cpu-defs.h"
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#include "elf.h"
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#include "hw/loader.h"
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#include "hw/openrisc/boot.h"
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#include "sysemu/device_tree.h"
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#include "sysemu/qtest.h"
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#include <libfdt.h>
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#define KERNEL_LOAD_ADDR 0x100
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hwaddr openrisc_load_kernel(ram_addr_t ram_size,
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const char *kernel_filename,
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uint32_t *bootstrap_pc)
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{
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long kernel_size;
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uint64_t elf_entry;
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uint64_t high_addr;
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hwaddr entry;
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||||
|
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if (kernel_filename && !qtest_enabled()) {
|
||||
kernel_size = load_elf(kernel_filename, NULL, NULL, NULL,
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&elf_entry, NULL, &high_addr, NULL, 1,
|
||||
EM_OPENRISC, 1, 0);
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entry = elf_entry;
|
||||
if (kernel_size < 0) {
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kernel_size = load_uimage(kernel_filename,
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&entry, NULL, NULL, NULL, NULL);
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high_addr = entry + kernel_size;
|
||||
}
|
||||
if (kernel_size < 0) {
|
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kernel_size = load_image_targphys(kernel_filename,
|
||||
KERNEL_LOAD_ADDR,
|
||||
ram_size - KERNEL_LOAD_ADDR);
|
||||
high_addr = KERNEL_LOAD_ADDR + kernel_size;
|
||||
}
|
||||
|
||||
if (entry <= 0) {
|
||||
entry = KERNEL_LOAD_ADDR;
|
||||
}
|
||||
|
||||
if (kernel_size < 0) {
|
||||
error_report("couldn't load the kernel '%s'", kernel_filename);
|
||||
exit(1);
|
||||
}
|
||||
*bootstrap_pc = entry;
|
||||
|
||||
return high_addr;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
hwaddr openrisc_load_initrd(void *fdt, const char *filename,
|
||||
hwaddr load_start, uint64_t mem_size)
|
||||
{
|
||||
int size;
|
||||
hwaddr start;
|
||||
|
||||
/* We put the initrd right after the kernel; page aligned. */
|
||||
start = TARGET_PAGE_ALIGN(load_start);
|
||||
|
||||
size = load_ramdisk(filename, start, mem_size - start);
|
||||
if (size < 0) {
|
||||
size = load_image_targphys(filename, start, mem_size - start);
|
||||
if (size < 0) {
|
||||
error_report("could not load ramdisk '%s'", filename);
|
||||
exit(1);
|
||||
}
|
||||
}
|
||||
|
||||
if (fdt) {
|
||||
qemu_fdt_setprop_cell(fdt, "/chosen",
|
||||
"linux,initrd-start", start);
|
||||
qemu_fdt_setprop_cell(fdt, "/chosen",
|
||||
"linux,initrd-end", start + size);
|
||||
}
|
||||
|
||||
return start + size;
|
||||
}
|
||||
|
||||
uint32_t openrisc_load_fdt(void *fdt, hwaddr load_start,
|
||||
uint64_t mem_size)
|
||||
{
|
||||
uint32_t fdt_addr;
|
||||
int ret;
|
||||
int fdtsize = fdt_totalsize(fdt);
|
||||
|
||||
if (fdtsize <= 0) {
|
||||
error_report("invalid device-tree");
|
||||
exit(1);
|
||||
}
|
||||
|
||||
/* We put fdt right after the kernel and/or initrd. */
|
||||
fdt_addr = TARGET_PAGE_ALIGN(load_start);
|
||||
|
||||
ret = fdt_pack(fdt);
|
||||
/* Should only fail if we've built a corrupted tree */
|
||||
g_assert(ret == 0);
|
||||
/* copy in the device tree */
|
||||
qemu_fdt_dumpdtb(fdt, fdtsize);
|
||||
|
||||
rom_add_blob_fixed_as("fdt", fdt, fdtsize, fdt_addr,
|
||||
&address_space_memory);
|
||||
|
||||
return fdt_addr;
|
||||
}
|
||||
|
|
@ -22,6 +22,7 @@
|
|||
#include "cpu.h"
|
||||
#include "migration/vmstate.h"
|
||||
#include "qemu/timer.h"
|
||||
#include "sysemu/reset.h"
|
||||
|
||||
#define TIMER_PERIOD 50 /* 50 ns period for 20 MHz timer */
|
||||
|
||||
|
|
@ -122,6 +123,24 @@ static void openrisc_timer_cb(void *opaque)
|
|||
qemu_cpu_kick(CPU(cpu));
|
||||
}
|
||||
|
||||
/* Reset the per CPU counter state. */
|
||||
static void openrisc_count_reset(void *opaque)
|
||||
{
|
||||
OpenRISCCPU *cpu = opaque;
|
||||
|
||||
if (cpu->env.is_counting) {
|
||||
cpu_openrisc_count_stop(cpu);
|
||||
}
|
||||
cpu->env.ttmr = 0x00000000;
|
||||
}
|
||||
|
||||
/* Reset the global timer state. */
|
||||
static void openrisc_timer_reset(void *opaque)
|
||||
{
|
||||
or1k_timer->ttcr = 0x00000000;
|
||||
or1k_timer->last_clk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
|
||||
}
|
||||
|
||||
static const VMStateDescription vmstate_or1k_timer = {
|
||||
.name = "or1k_timer",
|
||||
.version_id = 1,
|
||||
|
|
@ -136,10 +155,11 @@ static const VMStateDescription vmstate_or1k_timer = {
|
|||
void cpu_openrisc_clock_init(OpenRISCCPU *cpu)
|
||||
{
|
||||
cpu->env.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &openrisc_timer_cb, cpu);
|
||||
cpu->env.ttmr = 0x00000000;
|
||||
|
||||
qemu_register_reset(openrisc_count_reset, cpu);
|
||||
if (or1k_timer == NULL) {
|
||||
or1k_timer = g_new0(OR1KTimerState, 1);
|
||||
qemu_register_reset(openrisc_timer_reset, cpu);
|
||||
vmstate_register(NULL, 0, &vmstate_or1k_timer, or1k_timer);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,7 @@
|
|||
openrisc_ss = ss.source_set()
|
||||
openrisc_ss.add(files('cputimer.c'))
|
||||
openrisc_ss.add(files('boot.c'))
|
||||
openrisc_ss.add(when: 'CONFIG_OR1K_SIM', if_true: [files('openrisc_sim.c'), fdt])
|
||||
openrisc_ss.add(when: 'CONFIG_OR1K_VIRT', if_true: [files('virt.c'), fdt])
|
||||
|
||||
hw_arch += {'openrisc': openrisc_ss}
|
||||
|
|
|
|||
|
|
@ -24,10 +24,9 @@
|
|||
#include "cpu.h"
|
||||
#include "hw/irq.h"
|
||||
#include "hw/boards.h"
|
||||
#include "elf.h"
|
||||
#include "hw/char/serial.h"
|
||||
#include "net/net.h"
|
||||
#include "hw/loader.h"
|
||||
#include "hw/openrisc/boot.h"
|
||||
#include "hw/qdev-properties.h"
|
||||
#include "exec/address-spaces.h"
|
||||
#include "sysemu/device_tree.h"
|
||||
|
|
@ -283,101 +282,6 @@ static void openrisc_sim_serial_init(Or1ksimState *state, hwaddr base,
|
|||
g_free(nodename);
|
||||
}
|
||||
|
||||
static hwaddr openrisc_load_kernel(ram_addr_t ram_size,
|
||||
const char *kernel_filename)
|
||||
{
|
||||
long kernel_size;
|
||||
uint64_t elf_entry;
|
||||
uint64_t high_addr;
|
||||
hwaddr entry;
|
||||
|
||||
if (kernel_filename && !qtest_enabled()) {
|
||||
kernel_size = load_elf(kernel_filename, NULL, NULL, NULL,
|
||||
&elf_entry, NULL, &high_addr, NULL, 1,
|
||||
EM_OPENRISC, 1, 0);
|
||||
entry = elf_entry;
|
||||
if (kernel_size < 0) {
|
||||
kernel_size = load_uimage(kernel_filename,
|
||||
&entry, NULL, NULL, NULL, NULL);
|
||||
high_addr = entry + kernel_size;
|
||||
}
|
||||
if (kernel_size < 0) {
|
||||
kernel_size = load_image_targphys(kernel_filename,
|
||||
KERNEL_LOAD_ADDR,
|
||||
ram_size - KERNEL_LOAD_ADDR);
|
||||
high_addr = KERNEL_LOAD_ADDR + kernel_size;
|
||||
}
|
||||
|
||||
if (entry <= 0) {
|
||||
entry = KERNEL_LOAD_ADDR;
|
||||
}
|
||||
|
||||
if (kernel_size < 0) {
|
||||
error_report("couldn't load the kernel '%s'", kernel_filename);
|
||||
exit(1);
|
||||
}
|
||||
boot_info.bootstrap_pc = entry;
|
||||
|
||||
return high_addr;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static hwaddr openrisc_load_initrd(Or1ksimState *state, const char *filename,
|
||||
hwaddr load_start, uint64_t mem_size)
|
||||
{
|
||||
void *fdt = state->fdt;
|
||||
int size;
|
||||
hwaddr start;
|
||||
|
||||
/* We put the initrd right after the kernel; page aligned. */
|
||||
start = TARGET_PAGE_ALIGN(load_start);
|
||||
|
||||
size = load_ramdisk(filename, start, mem_size - start);
|
||||
if (size < 0) {
|
||||
size = load_image_targphys(filename, start, mem_size - start);
|
||||
if (size < 0) {
|
||||
error_report("could not load ramdisk '%s'", filename);
|
||||
exit(1);
|
||||
}
|
||||
}
|
||||
|
||||
qemu_fdt_setprop_cell(fdt, "/chosen",
|
||||
"linux,initrd-start", start);
|
||||
qemu_fdt_setprop_cell(fdt, "/chosen",
|
||||
"linux,initrd-end", start + size);
|
||||
|
||||
return start + size;
|
||||
}
|
||||
|
||||
static uint32_t openrisc_load_fdt(Or1ksimState *state, hwaddr load_start,
|
||||
uint64_t mem_size)
|
||||
{
|
||||
void *fdt = state->fdt;
|
||||
uint32_t fdt_addr;
|
||||
int ret;
|
||||
int fdtsize = fdt_totalsize(fdt);
|
||||
|
||||
if (fdtsize <= 0) {
|
||||
error_report("invalid device-tree");
|
||||
exit(1);
|
||||
}
|
||||
|
||||
/* We put fdt right after the kernel and/or initrd. */
|
||||
fdt_addr = TARGET_PAGE_ALIGN(load_start);
|
||||
|
||||
ret = fdt_pack(fdt);
|
||||
/* Should only fail if we've built a corrupted tree */
|
||||
g_assert(ret == 0);
|
||||
/* copy in the device tree */
|
||||
qemu_fdt_dumpdtb(fdt, fdtsize);
|
||||
|
||||
rom_add_blob_fixed_as("fdt", fdt, fdtsize, fdt_addr,
|
||||
&address_space_memory);
|
||||
|
||||
return fdt_addr;
|
||||
}
|
||||
|
||||
static void openrisc_sim_init(MachineState *machine)
|
||||
{
|
||||
ram_addr_t ram_size = machine->ram_size;
|
||||
|
|
@ -428,13 +332,15 @@ static void openrisc_sim_init(MachineState *machine)
|
|||
or1ksim_memmap[OR1KSIM_UART].size,
|
||||
smp_cpus, cpus, OR1KSIM_UART_IRQ, n);
|
||||
|
||||
load_addr = openrisc_load_kernel(ram_size, kernel_filename);
|
||||
load_addr = openrisc_load_kernel(ram_size, kernel_filename,
|
||||
&boot_info.bootstrap_pc);
|
||||
if (load_addr > 0) {
|
||||
if (machine->initrd_filename) {
|
||||
load_addr = openrisc_load_initrd(state, machine->initrd_filename,
|
||||
load_addr = openrisc_load_initrd(state->fdt,
|
||||
machine->initrd_filename,
|
||||
load_addr, machine->ram_size);
|
||||
}
|
||||
boot_info.fdt_addr = openrisc_load_fdt(state, load_addr,
|
||||
boot_info.fdt_addr = openrisc_load_fdt(state->fdt, load_addr,
|
||||
machine->ram_size);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -0,0 +1,571 @@
|
|||
/*
|
||||
* SPDX-License-Identifier: GPL-2.0-or-later
|
||||
*
|
||||
* OpenRISC QEMU virtual machine.
|
||||
*
|
||||
* (c) 2022 Stafford Horne <shorne@gmail.com>
|
||||
*/
|
||||
|
||||
#include "qemu/osdep.h"
|
||||
#include "qemu/error-report.h"
|
||||
#include "qemu/guest-random.h"
|
||||
#include "qapi/error.h"
|
||||
#include "cpu.h"
|
||||
#include "exec/address-spaces.h"
|
||||
#include "hw/irq.h"
|
||||
#include "hw/boards.h"
|
||||
#include "hw/char/serial.h"
|
||||
#include "hw/core/split-irq.h"
|
||||
#include "hw/openrisc/boot.h"
|
||||
#include "hw/misc/sifive_test.h"
|
||||
#include "hw/pci/pci.h"
|
||||
#include "hw/pci-host/gpex.h"
|
||||
#include "hw/qdev-properties.h"
|
||||
#include "hw/rtc/goldfish_rtc.h"
|
||||
#include "hw/sysbus.h"
|
||||
#include "hw/virtio/virtio-mmio.h"
|
||||
#include "sysemu/device_tree.h"
|
||||
#include "sysemu/sysemu.h"
|
||||
#include "sysemu/qtest.h"
|
||||
#include "sysemu/reset.h"
|
||||
|
||||
#include <libfdt.h>
|
||||
|
||||
#define VIRT_CPUS_MAX 4
|
||||
#define VIRT_CLK_MHZ 20000000
|
||||
|
||||
#define TYPE_VIRT_MACHINE MACHINE_TYPE_NAME("virt")
|
||||
#define VIRT_MACHINE(obj) \
|
||||
OBJECT_CHECK(OR1KVirtState, (obj), TYPE_VIRT_MACHINE)
|
||||
|
||||
typedef struct OR1KVirtState {
|
||||
/*< private >*/
|
||||
MachineState parent_obj;
|
||||
|
||||
/*< public >*/
|
||||
void *fdt;
|
||||
int fdt_size;
|
||||
|
||||
} OR1KVirtState;
|
||||
|
||||
enum {
|
||||
VIRT_DRAM,
|
||||
VIRT_ECAM,
|
||||
VIRT_MMIO,
|
||||
VIRT_PIO,
|
||||
VIRT_TEST,
|
||||
VIRT_RTC,
|
||||
VIRT_VIRTIO,
|
||||
VIRT_UART,
|
||||
VIRT_OMPIC,
|
||||
};
|
||||
|
||||
enum {
|
||||
VIRT_OMPIC_IRQ = 1,
|
||||
VIRT_UART_IRQ = 2,
|
||||
VIRT_RTC_IRQ = 3,
|
||||
VIRT_VIRTIO_IRQ = 4, /* to 12 */
|
||||
VIRTIO_COUNT = 8,
|
||||
VIRT_PCI_IRQ_BASE = 13, /* to 17 */
|
||||
};
|
||||
|
||||
static const struct MemmapEntry {
|
||||
hwaddr base;
|
||||
hwaddr size;
|
||||
} virt_memmap[] = {
|
||||
[VIRT_DRAM] = { 0x00000000, 0 },
|
||||
[VIRT_UART] = { 0x90000000, 0x100 },
|
||||
[VIRT_TEST] = { 0x96000000, 0x8 },
|
||||
[VIRT_RTC] = { 0x96005000, 0x1000 },
|
||||
[VIRT_VIRTIO] = { 0x97000000, 0x1000 },
|
||||
[VIRT_OMPIC] = { 0x98000000, VIRT_CPUS_MAX * 8 },
|
||||
[VIRT_ECAM] = { 0x9e000000, 0x1000000 },
|
||||
[VIRT_PIO] = { 0x9f000000, 0x1000000 },
|
||||
[VIRT_MMIO] = { 0xa0000000, 0x10000000 },
|
||||
};
|
||||
|
||||
static struct openrisc_boot_info {
|
||||
uint32_t bootstrap_pc;
|
||||
uint32_t fdt_addr;
|
||||
} boot_info;
|
||||
|
||||
static void main_cpu_reset(void *opaque)
|
||||
{
|
||||
OpenRISCCPU *cpu = opaque;
|
||||
CPUState *cs = CPU(cpu);
|
||||
|
||||
cpu_reset(CPU(cpu));
|
||||
|
||||
cpu_set_pc(cs, boot_info.bootstrap_pc);
|
||||
cpu_set_gpr(&cpu->env, 3, boot_info.fdt_addr);
|
||||
}
|
||||
|
||||
static qemu_irq get_cpu_irq(OpenRISCCPU *cpus[], int cpunum, int irq_pin)
|
||||
{
|
||||
return qdev_get_gpio_in_named(DEVICE(cpus[cpunum]), "IRQ", irq_pin);
|
||||
}
|
||||
|
||||
static qemu_irq get_per_cpu_irq(OpenRISCCPU *cpus[], int num_cpus, int irq_pin)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (num_cpus > 1) {
|
||||
DeviceState *splitter = qdev_new(TYPE_SPLIT_IRQ);
|
||||
qdev_prop_set_uint32(splitter, "num-lines", num_cpus);
|
||||
qdev_realize_and_unref(splitter, NULL, &error_fatal);
|
||||
for (i = 0; i < num_cpus; i++) {
|
||||
qdev_connect_gpio_out(splitter, i, get_cpu_irq(cpus, i, irq_pin));
|
||||
}
|
||||
return qdev_get_gpio_in(splitter, 0);
|
||||
} else {
|
||||
return get_cpu_irq(cpus, 0, irq_pin);
|
||||
}
|
||||
}
|
||||
|
||||
static void openrisc_create_fdt(OR1KVirtState *state,
|
||||
const struct MemmapEntry *memmap,
|
||||
int num_cpus, uint64_t mem_size,
|
||||
const char *cmdline,
|
||||
int32_t *pic_phandle)
|
||||
{
|
||||
void *fdt;
|
||||
int cpu;
|
||||
char *nodename;
|
||||
uint8_t rng_seed[32];
|
||||
|
||||
fdt = state->fdt = create_device_tree(&state->fdt_size);
|
||||
if (!fdt) {
|
||||
error_report("create_device_tree() failed");
|
||||
exit(1);
|
||||
}
|
||||
|
||||
qemu_fdt_setprop_string(fdt, "/", "compatible", "opencores,or1ksim");
|
||||
qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x1);
|
||||
qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x1);
|
||||
|
||||
qemu_fdt_add_subnode(fdt, "/soc");
|
||||
qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
|
||||
qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
|
||||
qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x1);
|
||||
qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x1);
|
||||
|
||||
nodename = g_strdup_printf("/memory@%" HWADDR_PRIx,
|
||||
memmap[VIRT_DRAM].base);
|
||||
qemu_fdt_add_subnode(fdt, nodename);
|
||||
qemu_fdt_setprop_cells(fdt, nodename, "reg",
|
||||
memmap[VIRT_DRAM].base, mem_size);
|
||||
qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
|
||||
g_free(nodename);
|
||||
|
||||
qemu_fdt_add_subnode(fdt, "/cpus");
|
||||
qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
|
||||
qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
|
||||
|
||||
for (cpu = 0; cpu < num_cpus; cpu++) {
|
||||
nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
|
||||
qemu_fdt_add_subnode(fdt, nodename);
|
||||
qemu_fdt_setprop_string(fdt, nodename, "compatible",
|
||||
"opencores,or1200-rtlsvn481");
|
||||
qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
|
||||
qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
|
||||
VIRT_CLK_MHZ);
|
||||
g_free(nodename);
|
||||
}
|
||||
|
||||
nodename = (char *)"/pic";
|
||||
qemu_fdt_add_subnode(fdt, nodename);
|
||||
*pic_phandle = qemu_fdt_alloc_phandle(fdt);
|
||||
qemu_fdt_setprop_string(fdt, nodename, "compatible",
|
||||
"opencores,or1k-pic-level");
|
||||
qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
|
||||
qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
|
||||
qemu_fdt_setprop_cell(fdt, nodename, "phandle", *pic_phandle);
|
||||
|
||||
qemu_fdt_setprop_cell(fdt, "/", "interrupt-parent", *pic_phandle);
|
||||
|
||||
qemu_fdt_add_subnode(fdt, "/chosen");
|
||||
if (cmdline) {
|
||||
qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
|
||||
}
|
||||
|
||||
/* Pass seed to RNG. */
|
||||
qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed));
|
||||
qemu_fdt_setprop(fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_seed));
|
||||
|
||||
/* Create aliases node for use by devices. */
|
||||
qemu_fdt_add_subnode(fdt, "/aliases");
|
||||
}
|
||||
|
||||
static void openrisc_virt_ompic_init(OR1KVirtState *state, hwaddr base,
|
||||
hwaddr size, int num_cpus,
|
||||
OpenRISCCPU *cpus[], int irq_pin)
|
||||
{
|
||||
void *fdt = state->fdt;
|
||||
DeviceState *dev;
|
||||
SysBusDevice *s;
|
||||
char *nodename;
|
||||
int i;
|
||||
|
||||
dev = qdev_new("or1k-ompic");
|
||||
qdev_prop_set_uint32(dev, "num-cpus", num_cpus);
|
||||
|
||||
s = SYS_BUS_DEVICE(dev);
|
||||
sysbus_realize_and_unref(s, &error_fatal);
|
||||
for (i = 0; i < num_cpus; i++) {
|
||||
sysbus_connect_irq(s, i, get_cpu_irq(cpus, i, irq_pin));
|
||||
}
|
||||
sysbus_mmio_map(s, 0, base);
|
||||
|
||||
/* Add device tree node for ompic. */
|
||||
nodename = g_strdup_printf("/ompic@%" HWADDR_PRIx, base);
|
||||
qemu_fdt_add_subnode(fdt, nodename);
|
||||
qemu_fdt_setprop_string(fdt, nodename, "compatible", "openrisc,ompic");
|
||||
qemu_fdt_setprop_cells(fdt, nodename, "reg", base, size);
|
||||
qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
|
||||
qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 0);
|
||||
qemu_fdt_setprop_cell(fdt, nodename, "interrupts", irq_pin);
|
||||
g_free(nodename);
|
||||
}
|
||||
|
||||
static void openrisc_virt_serial_init(OR1KVirtState *state, hwaddr base,
|
||||
hwaddr size, int num_cpus,
|
||||
OpenRISCCPU *cpus[], int irq_pin)
|
||||
{
|
||||
void *fdt = state->fdt;
|
||||
char *nodename;
|
||||
qemu_irq serial_irq = get_per_cpu_irq(cpus, num_cpus, irq_pin);
|
||||
|
||||
serial_mm_init(get_system_memory(), base, 0, serial_irq, 115200,
|
||||
serial_hd(0), DEVICE_NATIVE_ENDIAN);
|
||||
|
||||
/* Add device tree node for serial. */
|
||||
nodename = g_strdup_printf("/serial@%" HWADDR_PRIx, base);
|
||||
qemu_fdt_add_subnode(fdt, nodename);
|
||||
qemu_fdt_setprop_string(fdt, nodename, "compatible", "ns16550a");
|
||||
qemu_fdt_setprop_cells(fdt, nodename, "reg", base, size);
|
||||
qemu_fdt_setprop_cell(fdt, nodename, "interrupts", irq_pin);
|
||||
qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", VIRT_CLK_MHZ);
|
||||
qemu_fdt_setprop(fdt, nodename, "big-endian", NULL, 0);
|
||||
|
||||
/* The /chosen node is created during fdt creation. */
|
||||
qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
|
||||
qemu_fdt_setprop_string(fdt, "/aliases", "uart0", nodename);
|
||||
g_free(nodename);
|
||||
}
|
||||
|
||||
static void openrisc_virt_test_init(OR1KVirtState *state, hwaddr base,
|
||||
hwaddr size)
|
||||
{
|
||||
void *fdt = state->fdt;
|
||||
int test_ph;
|
||||
char *nodename;
|
||||
|
||||
/* SiFive Test MMIO device */
|
||||
sifive_test_create(base);
|
||||
|
||||
/* SiFive Test MMIO Reset device FDT */
|
||||
nodename = g_strdup_printf("/soc/test@%" HWADDR_PRIx, base);
|
||||
qemu_fdt_add_subnode(fdt, nodename);
|
||||
qemu_fdt_setprop_string(fdt, nodename, "compatible", "syscon");
|
||||
test_ph = qemu_fdt_alloc_phandle(fdt);
|
||||
qemu_fdt_setprop_cells(fdt, nodename, "reg", base, size);
|
||||
qemu_fdt_setprop_cell(fdt, nodename, "phandle", test_ph);
|
||||
qemu_fdt_setprop(fdt, nodename, "big-endian", NULL, 0);
|
||||
g_free(nodename);
|
||||
|
||||
nodename = g_strdup_printf("/soc/reboot");
|
||||
qemu_fdt_add_subnode(fdt, nodename);
|
||||
qemu_fdt_setprop_string(fdt, nodename, "compatible", "syscon-reboot");
|
||||
qemu_fdt_setprop_cell(fdt, nodename, "regmap", test_ph);
|
||||
qemu_fdt_setprop_cell(fdt, nodename, "offset", 0x0);
|
||||
qemu_fdt_setprop_cell(fdt, nodename, "value", FINISHER_RESET);
|
||||
g_free(nodename);
|
||||
|
||||
nodename = g_strdup_printf("/soc/poweroff");
|
||||
qemu_fdt_add_subnode(fdt, nodename);
|
||||
qemu_fdt_setprop_string(fdt, nodename, "compatible", "syscon-poweroff");
|
||||
qemu_fdt_setprop_cell(fdt, nodename, "regmap", test_ph);
|
||||
qemu_fdt_setprop_cell(fdt, nodename, "offset", 0x0);
|
||||
qemu_fdt_setprop_cell(fdt, nodename, "value", FINISHER_PASS);
|
||||
g_free(nodename);
|
||||
|
||||
}
|
||||
|
||||
static void openrisc_virt_rtc_init(OR1KVirtState *state, hwaddr base,
|
||||
hwaddr size, int num_cpus,
|
||||
OpenRISCCPU *cpus[], int irq_pin)
|
||||
{
|
||||
void *fdt = state->fdt;
|
||||
char *nodename;
|
||||
qemu_irq rtc_irq = get_per_cpu_irq(cpus, num_cpus, irq_pin);
|
||||
|
||||
/* Goldfish RTC */
|
||||
sysbus_create_simple(TYPE_GOLDFISH_RTC, base, rtc_irq);
|
||||
|
||||
/* Goldfish RTC FDT */
|
||||
nodename = g_strdup_printf("/soc/rtc@%" HWADDR_PRIx, base);
|
||||
qemu_fdt_add_subnode(fdt, nodename);
|
||||
qemu_fdt_setprop_string(fdt, nodename, "compatible",
|
||||
"google,goldfish-rtc");
|
||||
qemu_fdt_setprop_cells(fdt, nodename, "reg", base, size);
|
||||
qemu_fdt_setprop_cell(fdt, nodename, "interrupts", irq_pin);
|
||||
g_free(nodename);
|
||||
|
||||
}
|
||||
|
||||
static void create_pcie_irq_map(void *fdt, char *nodename, int irq_base,
|
||||
uint32_t irqchip_phandle)
|
||||
{
|
||||
int pin, dev;
|
||||
uint32_t irq_map_stride = 0;
|
||||
uint32_t full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * 6] = {};
|
||||
uint32_t *irq_map = full_irq_map;
|
||||
|
||||
/*
|
||||
* This code creates a standard swizzle of interrupts such that
|
||||
* each device's first interrupt is based on it's PCI_SLOT number.
|
||||
* (See pci_swizzle_map_irq_fn())
|
||||
*
|
||||
* We only need one entry per interrupt in the table (not one per
|
||||
* possible slot) seeing the interrupt-map-mask will allow the table
|
||||
* to wrap to any number of devices.
|
||||
*/
|
||||
for (dev = 0; dev < GPEX_NUM_IRQS; dev++) {
|
||||
int devfn = dev << 3;
|
||||
|
||||
for (pin = 0; pin < GPEX_NUM_IRQS; pin++) {
|
||||
int irq_nr = irq_base + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS);
|
||||
int i = 0;
|
||||
|
||||
/* Fill PCI address cells */
|
||||
irq_map[i++] = cpu_to_be32(devfn << 8);
|
||||
irq_map[i++] = 0;
|
||||
irq_map[i++] = 0;
|
||||
|
||||
/* Fill PCI Interrupt cells */
|
||||
irq_map[i++] = cpu_to_be32(pin + 1);
|
||||
|
||||
/* Fill interrupt controller phandle and cells */
|
||||
irq_map[i++] = cpu_to_be32(irqchip_phandle);
|
||||
irq_map[i++] = cpu_to_be32(irq_nr);
|
||||
|
||||
if (!irq_map_stride) {
|
||||
irq_map_stride = i;
|
||||
}
|
||||
irq_map += irq_map_stride;
|
||||
}
|
||||
}
|
||||
|
||||
qemu_fdt_setprop(fdt, nodename, "interrupt-map", full_irq_map,
|
||||
GPEX_NUM_IRQS * GPEX_NUM_IRQS *
|
||||
irq_map_stride * sizeof(uint32_t));
|
||||
|
||||
qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask",
|
||||
0x1800, 0, 0, 0x7);
|
||||
}
|
||||
|
||||
static void openrisc_virt_pcie_init(OR1KVirtState *state,
|
||||
hwaddr ecam_base, hwaddr ecam_size,
|
||||
hwaddr pio_base, hwaddr pio_size,
|
||||
hwaddr mmio_base, hwaddr mmio_size,
|
||||
int num_cpus, OpenRISCCPU *cpus[],
|
||||
int irq_base, int32_t pic_phandle)
|
||||
{
|
||||
void *fdt = state->fdt;
|
||||
char *nodename;
|
||||
MemoryRegion *alias;
|
||||
MemoryRegion *reg;
|
||||
DeviceState *dev;
|
||||
qemu_irq pcie_irq;
|
||||
int i;
|
||||
|
||||
dev = qdev_new(TYPE_GPEX_HOST);
|
||||
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
|
||||
|
||||
/* Map ECAM space. */
|
||||
alias = g_new0(MemoryRegion, 1);
|
||||
reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
|
||||
memory_region_init_alias(alias, OBJECT(dev), "pcie-ecam",
|
||||
reg, 0, ecam_size);
|
||||
memory_region_add_subregion(get_system_memory(), ecam_base, alias);
|
||||
|
||||
/*
|
||||
* Map the MMIO window into system address space so as to expose
|
||||
* the section of PCI MMIO space which starts at the same base address
|
||||
* (ie 1:1 mapping for that part of PCI MMIO space visible through
|
||||
* the window).
|
||||
*/
|
||||
alias = g_new0(MemoryRegion, 1);
|
||||
reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
|
||||
memory_region_init_alias(alias, OBJECT(dev), "pcie-mmio",
|
||||
reg, mmio_base, mmio_size);
|
||||
memory_region_add_subregion(get_system_memory(), mmio_base, alias);
|
||||
|
||||
/* Map IO port space. */
|
||||
alias = g_new0(MemoryRegion, 1);
|
||||
reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 2);
|
||||
memory_region_init_alias(alias, OBJECT(dev), "pcie-pio",
|
||||
reg, 0, pio_size);
|
||||
memory_region_add_subregion(get_system_memory(), pio_base, alias);
|
||||
|
||||
/* Connect IRQ lines. */
|
||||
for (i = 0; i < GPEX_NUM_IRQS; i++) {
|
||||
pcie_irq = get_per_cpu_irq(cpus, num_cpus, irq_base + i);
|
||||
|
||||
sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pcie_irq);
|
||||
gpex_set_irq_num(GPEX_HOST(dev), i, irq_base + i);
|
||||
}
|
||||
|
||||
nodename = g_strdup_printf("/soc/pci@%" HWADDR_PRIx, ecam_base);
|
||||
qemu_fdt_add_subnode(fdt, nodename);
|
||||
qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
|
||||
qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 3);
|
||||
qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 2);
|
||||
qemu_fdt_setprop_string(fdt, nodename, "compatible",
|
||||
"pci-host-ecam-generic");
|
||||
qemu_fdt_setprop_string(fdt, nodename, "device_type", "pci");
|
||||
qemu_fdt_setprop_cell(fdt, nodename, "linux,pci-domain", 0);
|
||||
qemu_fdt_setprop_cells(fdt, nodename, "bus-range", 0,
|
||||
ecam_size / PCIE_MMCFG_SIZE_MIN - 1);
|
||||
qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0);
|
||||
qemu_fdt_setprop_cells(fdt, nodename, "reg", ecam_base, ecam_size);
|
||||
/* pci-address(3) cpu-address(1) pci-size(2) */
|
||||
qemu_fdt_setprop_cells(fdt, nodename, "ranges",
|
||||
FDT_PCI_RANGE_IOPORT, 0, 0,
|
||||
pio_base, 0, pio_size,
|
||||
FDT_PCI_RANGE_MMIO, 0, mmio_base,
|
||||
mmio_base, 0, mmio_size);
|
||||
|
||||
create_pcie_irq_map(fdt, nodename, irq_base, pic_phandle);
|
||||
g_free(nodename);
|
||||
}
|
||||
|
||||
static void openrisc_virt_virtio_init(OR1KVirtState *state, hwaddr base,
|
||||
hwaddr size, int num_cpus,
|
||||
OpenRISCCPU *cpus[], int irq_pin)
|
||||
{
|
||||
void *fdt = state->fdt;
|
||||
char *nodename;
|
||||
DeviceState *dev;
|
||||
SysBusDevice *sysbus;
|
||||
qemu_irq virtio_irq = get_per_cpu_irq(cpus, num_cpus, irq_pin);
|
||||
|
||||
/* VirtIO MMIO devices */
|
||||
dev = qdev_new(TYPE_VIRTIO_MMIO);
|
||||
qdev_prop_set_bit(dev, "force-legacy", false);
|
||||
sysbus = SYS_BUS_DEVICE(dev);
|
||||
sysbus_realize_and_unref(sysbus, &error_fatal);
|
||||
sysbus_connect_irq(sysbus, 0, virtio_irq);
|
||||
sysbus_mmio_map(sysbus, 0, base);
|
||||
|
||||
/* VirtIO MMIO devices FDT */
|
||||
nodename = g_strdup_printf("/soc/virtio_mmio@%" HWADDR_PRIx, base);
|
||||
qemu_fdt_add_subnode(fdt, nodename);
|
||||
qemu_fdt_setprop_string(fdt, nodename, "compatible", "virtio,mmio");
|
||||
qemu_fdt_setprop_cells(fdt, nodename, "reg", base, size);
|
||||
qemu_fdt_setprop_cell(fdt, nodename, "interrupts", irq_pin);
|
||||
g_free(nodename);
|
||||
}
|
||||
|
||||
static void openrisc_virt_init(MachineState *machine)
|
||||
{
|
||||
ram_addr_t ram_size = machine->ram_size;
|
||||
const char *kernel_filename = machine->kernel_filename;
|
||||
OpenRISCCPU *cpus[VIRT_CPUS_MAX] = {};
|
||||
OR1KVirtState *state = VIRT_MACHINE(machine);
|
||||
MemoryRegion *ram;
|
||||
hwaddr load_addr;
|
||||
int n;
|
||||
unsigned int smp_cpus = machine->smp.cpus;
|
||||
int32_t pic_phandle;
|
||||
|
||||
assert(smp_cpus >= 1 && smp_cpus <= VIRT_CPUS_MAX);
|
||||
for (n = 0; n < smp_cpus; n++) {
|
||||
cpus[n] = OPENRISC_CPU(cpu_create(machine->cpu_type));
|
||||
if (cpus[n] == NULL) {
|
||||
fprintf(stderr, "Unable to find CPU definition!\n");
|
||||
exit(1);
|
||||
}
|
||||
|
||||
cpu_openrisc_clock_init(cpus[n]);
|
||||
|
||||
qemu_register_reset(main_cpu_reset, cpus[n]);
|
||||
}
|
||||
|
||||
ram = g_malloc(sizeof(*ram));
|
||||
memory_region_init_ram(ram, NULL, "openrisc.ram", ram_size, &error_fatal);
|
||||
memory_region_add_subregion(get_system_memory(), 0, ram);
|
||||
|
||||
openrisc_create_fdt(state, virt_memmap, smp_cpus, machine->ram_size,
|
||||
machine->kernel_cmdline, &pic_phandle);
|
||||
|
||||
if (smp_cpus > 1) {
|
||||
openrisc_virt_ompic_init(state, virt_memmap[VIRT_OMPIC].base,
|
||||
virt_memmap[VIRT_OMPIC].size,
|
||||
smp_cpus, cpus, VIRT_OMPIC_IRQ);
|
||||
}
|
||||
|
||||
openrisc_virt_serial_init(state, virt_memmap[VIRT_UART].base,
|
||||
virt_memmap[VIRT_UART].size,
|
||||
smp_cpus, cpus, VIRT_UART_IRQ);
|
||||
|
||||
openrisc_virt_test_init(state, virt_memmap[VIRT_TEST].base,
|
||||
virt_memmap[VIRT_TEST].size);
|
||||
|
||||
openrisc_virt_rtc_init(state, virt_memmap[VIRT_RTC].base,
|
||||
virt_memmap[VIRT_RTC].size, smp_cpus, cpus,
|
||||
VIRT_RTC_IRQ);
|
||||
|
||||
openrisc_virt_pcie_init(state, virt_memmap[VIRT_ECAM].base,
|
||||
virt_memmap[VIRT_ECAM].size,
|
||||
virt_memmap[VIRT_PIO].base,
|
||||
virt_memmap[VIRT_PIO].size,
|
||||
virt_memmap[VIRT_MMIO].base,
|
||||
virt_memmap[VIRT_MMIO].size,
|
||||
smp_cpus, cpus,
|
||||
VIRT_PCI_IRQ_BASE, pic_phandle);
|
||||
|
||||
for (n = 0; n < VIRTIO_COUNT; n++) {
|
||||
openrisc_virt_virtio_init(state, virt_memmap[VIRT_VIRTIO].base
|
||||
+ n * virt_memmap[VIRT_VIRTIO].size,
|
||||
virt_memmap[VIRT_VIRTIO].size,
|
||||
smp_cpus, cpus, VIRT_VIRTIO_IRQ + n);
|
||||
}
|
||||
|
||||
load_addr = openrisc_load_kernel(ram_size, kernel_filename,
|
||||
&boot_info.bootstrap_pc);
|
||||
if (load_addr > 0) {
|
||||
if (machine->initrd_filename) {
|
||||
load_addr = openrisc_load_initrd(state->fdt,
|
||||
machine->initrd_filename,
|
||||
load_addr, machine->ram_size);
|
||||
}
|
||||
boot_info.fdt_addr = openrisc_load_fdt(state->fdt, load_addr,
|
||||
machine->ram_size);
|
||||
}
|
||||
}
|
||||
|
||||
static void openrisc_virt_machine_init(ObjectClass *oc, void *data)
|
||||
{
|
||||
MachineClass *mc = MACHINE_CLASS(oc);
|
||||
|
||||
mc->desc = "or1k virtual machine";
|
||||
mc->init = openrisc_virt_init;
|
||||
mc->max_cpus = VIRT_CPUS_MAX;
|
||||
mc->is_default = false;
|
||||
mc->default_cpu_type = OPENRISC_CPU_TYPE_NAME("or1200");
|
||||
}
|
||||
|
||||
static const TypeInfo or1ksim_machine_typeinfo = {
|
||||
.name = TYPE_VIRT_MACHINE,
|
||||
.parent = TYPE_MACHINE,
|
||||
.class_init = openrisc_virt_machine_init,
|
||||
.instance_size = sizeof(OR1KVirtState),
|
||||
};
|
||||
|
||||
static void or1ksim_machine_init_register_types(void)
|
||||
{
|
||||
type_register_static(&or1ksim_machine_typeinfo);
|
||||
}
|
||||
|
||||
type_init(or1ksim_machine_init_register_types)
|
||||
|
|
@ -216,14 +216,25 @@ static int goldfish_rtc_post_load(void *opaque, int version_id)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static const MemoryRegionOps goldfish_rtc_ops = {
|
||||
.read = goldfish_rtc_read,
|
||||
.write = goldfish_rtc_write,
|
||||
.endianness = DEVICE_NATIVE_ENDIAN,
|
||||
.valid = {
|
||||
.min_access_size = 4,
|
||||
.max_access_size = 4
|
||||
}
|
||||
static const MemoryRegionOps goldfish_rtc_ops[2] = {
|
||||
[false] = {
|
||||
.read = goldfish_rtc_read,
|
||||
.write = goldfish_rtc_write,
|
||||
.endianness = DEVICE_LITTLE_ENDIAN,
|
||||
.valid = {
|
||||
.min_access_size = 4,
|
||||
.max_access_size = 4
|
||||
}
|
||||
},
|
||||
[true] = {
|
||||
.read = goldfish_rtc_read,
|
||||
.write = goldfish_rtc_write,
|
||||
.endianness = DEVICE_BIG_ENDIAN,
|
||||
.valid = {
|
||||
.min_access_size = 4,
|
||||
.max_access_size = 4
|
||||
}
|
||||
},
|
||||
};
|
||||
|
||||
static const VMStateDescription goldfish_rtc_vmstate = {
|
||||
|
|
@ -265,7 +276,8 @@ static void goldfish_rtc_realize(DeviceState *d, Error **errp)
|
|||
SysBusDevice *dev = SYS_BUS_DEVICE(d);
|
||||
GoldfishRTCState *s = GOLDFISH_RTC(d);
|
||||
|
||||
memory_region_init_io(&s->iomem, OBJECT(s), &goldfish_rtc_ops, s,
|
||||
memory_region_init_io(&s->iomem, OBJECT(s),
|
||||
&goldfish_rtc_ops[s->big_endian], s,
|
||||
"goldfish_rtc", 0x24);
|
||||
sysbus_init_mmio(dev, &s->iomem);
|
||||
|
||||
|
|
@ -274,10 +286,17 @@ static void goldfish_rtc_realize(DeviceState *d, Error **errp)
|
|||
s->timer = timer_new_ns(rtc_clock, goldfish_rtc_interrupt, s);
|
||||
}
|
||||
|
||||
static Property goldfish_rtc_properties[] = {
|
||||
DEFINE_PROP_BOOL("big-endian", GoldfishRTCState, big_endian,
|
||||
false),
|
||||
DEFINE_PROP_END_OF_LIST(),
|
||||
};
|
||||
|
||||
static void goldfish_rtc_class_init(ObjectClass *klass, void *data)
|
||||
{
|
||||
DeviceClass *dc = DEVICE_CLASS(klass);
|
||||
|
||||
device_class_set_props(dc, goldfish_rtc_properties);
|
||||
dc->realize = goldfish_rtc_realize;
|
||||
dc->reset = goldfish_rtc_reset;
|
||||
dc->vmsd = &goldfish_rtc_vmstate;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,34 @@
|
|||
/*
|
||||
* QEMU OpenRISC boot helpers.
|
||||
*
|
||||
* Copyright (c) 2022 Stafford Horne <shorne@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2 or later, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef OPENRISC_BOOT_H
|
||||
#define OPENRISC_BOOT_H
|
||||
|
||||
#include "exec/cpu-defs.h"
|
||||
|
||||
hwaddr openrisc_load_kernel(ram_addr_t ram_size,
|
||||
const char *kernel_filename,
|
||||
uint32_t *bootstrap_pc);
|
||||
|
||||
hwaddr openrisc_load_initrd(void *fdt, const char *filename,
|
||||
hwaddr load_start, uint64_t mem_size);
|
||||
|
||||
uint32_t openrisc_load_fdt(void *fdt, hwaddr load_start,
|
||||
uint64_t mem_size);
|
||||
|
||||
#endif /* OPENRISC_BOOT_H */
|
||||
|
|
@ -42,6 +42,8 @@ struct GoldfishRTCState {
|
|||
uint32_t irq_pending;
|
||||
uint32_t irq_enabled;
|
||||
uint32_t time_high;
|
||||
|
||||
bool big_endian;
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -98,7 +98,6 @@ static void openrisc_cpu_set_irq(void *opaque, int irq, int level)
|
|||
cpu_interrupt(cs, CPU_INTERRUPT_HARD);
|
||||
} else {
|
||||
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
|
||||
cpu->env.picsr = 0;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -25,6 +25,8 @@
|
|||
#include "hw/core/cpu.h"
|
||||
#include "qom/object.h"
|
||||
|
||||
#define TCG_GUEST_DEFAULT_MO (0)
|
||||
|
||||
#define TYPE_OPENRISC_CPU "or1k-cpu"
|
||||
|
||||
OBJECT_DECLARE_CPU_TYPE(OpenRISCCPU, OpenRISCCPUClass, OPENRISC_CPU)
|
||||
|
|
|
|||
|
|
@ -83,7 +83,9 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
|
|||
[EXCP_TRAP] = "TRAP",
|
||||
};
|
||||
|
||||
qemu_log_mask(CPU_LOG_INT, "INT: %s\n", int_name[exception]);
|
||||
qemu_log_mask(CPU_LOG_INT, "CPU: %d INT: %s\n",
|
||||
cs->cpu_index,
|
||||
int_name[exception]);
|
||||
|
||||
hwaddr vect_pc = exception << 8;
|
||||
if (env->cpucfgr & CPUCFGR_EVBARP) {
|
||||
|
|
|
|||
|
|
@ -148,7 +148,13 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
|
|||
case SR_DME | SR_IME:
|
||||
/* The mmu is definitely enabled. */
|
||||
excp = get_phys_mmu(cpu, &phys_addr, &prot, addr,
|
||||
PAGE_EXEC | PAGE_READ | PAGE_WRITE,
|
||||
PAGE_READ,
|
||||
(sr & SR_SM) != 0);
|
||||
if (!excp) {
|
||||
return phys_addr;
|
||||
}
|
||||
excp = get_phys_mmu(cpu, &phys_addr, &prot, addr,
|
||||
PAGE_EXEC,
|
||||
(sr & SR_SM) != 0);
|
||||
return excp ? -1 : phys_addr;
|
||||
|
||||
|
|
|
|||
|
|
@ -139,12 +139,20 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
|
|||
break;
|
||||
case TO_SPR(9, 0): /* PICMR */
|
||||
env->picmr = rb;
|
||||
qemu_mutex_lock_iothread();
|
||||
if (env->picsr & env->picmr) {
|
||||
cpu_interrupt(cs, CPU_INTERRUPT_HARD);
|
||||
} else {
|
||||
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
|
||||
}
|
||||
qemu_mutex_unlock_iothread();
|
||||
break;
|
||||
case TO_SPR(9, 2): /* PICSR */
|
||||
env->picsr &= ~rb;
|
||||
break;
|
||||
case TO_SPR(10, 0): /* TTMR */
|
||||
{
|
||||
qemu_mutex_lock_iothread();
|
||||
if ((env->ttmr & TTMR_M) ^ (rb & TTMR_M)) {
|
||||
switch (rb & TTMR_M) {
|
||||
case TIMER_NONE:
|
||||
|
|
@ -168,14 +176,16 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
|
|||
env->ttmr = rb & ~TTMR_IP;
|
||||
cs->interrupt_request &= ~CPU_INTERRUPT_TIMER;
|
||||
}
|
||||
|
||||
cpu_openrisc_timer_update(cpu);
|
||||
qemu_mutex_unlock_iothread();
|
||||
}
|
||||
break;
|
||||
|
||||
case TO_SPR(10, 1): /* TTCR */
|
||||
qemu_mutex_lock_iothread();
|
||||
cpu_openrisc_count_set(cpu, rb);
|
||||
cpu_openrisc_timer_update(cpu);
|
||||
qemu_mutex_unlock_iothread();
|
||||
break;
|
||||
#endif
|
||||
|
||||
|
|
@ -303,7 +313,9 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd,
|
|||
return env->ttmr;
|
||||
|
||||
case TO_SPR(10, 1): /* TTCR */
|
||||
qemu_mutex_lock_iothread();
|
||||
cpu_openrisc_count_update(cpu);
|
||||
qemu_mutex_unlock_iothread();
|
||||
return cpu_openrisc_count_get(cpu);
|
||||
#endif
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue