From ff9f31d9a0d45da83f34207b7ccace850cfc465b Mon Sep 17 00:00:00 2001 From: Xi Wang Date: Sat, 26 Jan 2019 15:02:56 -0800 Subject: [PATCH] target/riscv: fix counter-enable checks in ctr() Access to a counter in U-mode is permitted only if the corresponding bit is set in both mcounteren and scounteren. The current code ignores mcounteren and checks scounteren only for U-mode access. Signed-off-by: Xi Wang Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target/riscv/csr.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index e72fcf1265..960d2b0aa9 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -56,9 +56,15 @@ static int fs(CPURISCVState *env, int csrno) static int ctr(CPURISCVState *env, int csrno) { #if !defined(CONFIG_USER_ONLY) - target_ulong ctr_en = env->priv == PRV_U ? env->scounteren : - env->priv == PRV_S ? env->mcounteren : -1U; - if (!(ctr_en & (1 << (csrno & 31)))) { + uint32_t ctr_en = ~0u; + + if (env->priv < PRV_M) { + ctr_en &= env->mcounteren; + } + if (env->priv < PRV_S) { + ctr_en &= env->scounteren; + } + if (!(ctr_en & (1u << (csrno & 31)))) { return -1; } #endif