vitalif
/
mirror_qemu
mirror of https://github.com/proxmox/mirror_qemu
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
42,906 Commits
1 Branch
49 Tags
416 MiB
Commit Graph

55 Commits (d8c02bcc9404b65e8cc290c009bf43f571ec967f)

Author SHA1 Message Date
Max Filippov 553e44f906 target-xtensa: implement windowed registers 
See ISA, 4.7.1 for details.

Physical registers and currently visible window are separate fields in
CPUEnv. Only current window is accessible to TCG. On operations that
change window base helpers copy current window to and from physical
registers.

Window overflow check described in 4.7.1.3 is in separate patch.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
 2011-09-10 16:57:39 +00:00
Max Filippov 40643d7c0f target-xtensa: implement exceptions 
- mark privileged opcodes with ring check;
- make debug exception on exception handler entry.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
 2011-09-10 16:57:38 +00:00
Max Filippov 3580ecad0a target-xtensa: implement shifts (ST1 and RST1 groups) 
- ST1: SAR (shift amount special register) manipulation, NSA(U);
- RST1: shifts, 16-bit multiplication.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
 2011-09-10 16:57:38 +00:00
Max Filippov dedc5eae23 target-xtensa: implement disas_xtensa_insn 
Set up disas_xtensa_insn switch structure, mark required options on high
level groups. Implement arithmetic/bit logic/jump/call0.

Implement code generation loop with single step/breakpoint checking.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
 2011-09-10 16:57:36 +00:00
Max Filippov 2328826b1d target-xtensa: add target stubs 
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
 2011-09-10 16:57:36 +00:00