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78 Commits (fc56ef08b9bb8cc1478fa0758c2bc65f1b6a9a79)

Author SHA1 Message Date
aliguori 6b9175478e Refactor translation block CPU state handling (Jan Kiszka) 
This patch refactors the way the CPU state is handled that is associated
with a TB. The basic motivation is to move more arch specific code out
of generic files. Specifically the long #ifdef clutter in tb_find_fast()
has to be overcome in order to avoid duplicating it for the gdb
watchpoint fixes (patch "Restore pc on watchpoint hits").

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5736 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-18 19:46:41 +00:00
aliguori 622ed3605b Convert CPU_PC_FROM_TB to static inline (Jan Kiszka) 
as macros should be avoided when possible.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5735 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-18 19:36:03 +00:00
aurel32 2623c1ecfc target-mips: optimize gen_op_addr_add() (2/2) 
Instead of dynamically generating different code depending on the UX
flag, add a new flag in ctx->flags to generate different code.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5677 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-11 11:39:33 +00:00
blueswir1 e18231a3ff Show size for unassigned accesses (Robert Reif) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5436 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-10-06 18:46:28 +00:00
ths f01be15458 Move the active FPU registers into env again, and use more TCG registers 
to access them.

Signed-off-by: Thiemo Seufer <ths@networkno.de>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5252 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-18 11:57:27 +00:00
ths 0eaef5aa01 Less hardcoding of TARGET_USER_ONLY. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4928 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-23 16:14:22 +00:00
ths b6d96beda3 Use temporary registers for the MIPS FPU emulation. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4861 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-09 11:05:10 +00:00
pbrook 9656f324d2 Move interrupt_request and user_mode_only to common cpu state. 
Save and restore env->interrupt_request and env->halted.



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4817 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-01 20:01:19 +00:00
pbrook b3c7724cbc Move CPU save/load registration to common code. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4808 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-30 16:31:04 +00:00
pbrook 2e70f6efa8 Add instruction counter. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4799 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-29 01:03:05 +00:00
ths b5dc7732e1 More efficient target register / TC accesses. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4794 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-27 10:02:35 +00:00
ths 1a3fd9c3da Remove remaining uses of T0 in the MIPS target. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4788 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-24 21:58:35 +00:00
ths e1bf387ec8 T1 is now dead. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4787 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-24 20:13:20 +00:00
ths 764dfc3fa0 Move FP TNs to cpu env. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4728 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-11 10:39:48 +00:00
pbrook f8ed7070ea Fix typo. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4624 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-30 17:54:15 +00:00
pbrook 6e68e076e7 Move clone() register setup to target specific code. Handle fork-like clone. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4623 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-30 17:22:15 +00:00
bellard 9133e39b84 Push common interrupt variables to cpu-defs.h (Glauber Costa) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4612 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-29 10:08:06 +00:00
bellard ce5232c5c2 moved halted field to CPU_COMMON 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4609 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-28 17:14:10 +00:00
ths 893f986502 Honour current_tc for MIPS M{T,F}{HI,LO}, by Richard Sandiford. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4604 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-28 13:37:19 +00:00
ths 958fb4a92c Use TCG for MIPS GPR moves. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4356 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-06 10:57:59 +00:00
ths 3945462805 Simplify mips branch handling. Retire T2 from use. Use TCG for branches. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4320 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-04 08:16:10 +00:00
ths d0dc7dc327 Make MIPS MT implementation more cache friendly. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3981 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-02-12 21:01:26 +00:00
ths b8aa4598e2 MIPS COP1X (and related) instructions, by Richard Sandiford. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3877 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-12-30 15:36:58 +00:00
ths 14e51cc7a4 De-cruft exception definitions, and implement nicer debug output. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3861 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-12-26 19:34:03 +00:00
ths 6d35524c40 Improved PABITS handling, and config register fixes. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3855 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-12-25 03:13:56 +00:00
bellard aaed909a49 added cpu_model parameter to cpu_init() 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3562 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-11-10 15:15:54 +00:00
ths 7df526e317 Move kernel loader parameters from the cpu state to being board specific. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3557 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-11-09 17:52:11 +00:00
ths 623a930ec3 Implement missing MIPS supervisor mode bits. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3472 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-10-28 19:45:05 +00:00
ths 647de6ca24 Handle IBE on MIPS properly. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3416 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-10-20 19:45:44 +00:00
j_mayer 6ebbf39000 Replace is_user variable with mmu_idx in softmmu core, 
allowing support of more than 2 mmu access modes.
Add backward compatibility is_user variable in targets code when needed.
Implement per target cpu_mmu_index function, avoiding duplicated code
  and #ifdef TARGET_xxx in softmmu core functions.
Implement per target mmu modes definitions. As an example, add PowerPC
  hypervisor mode definition and Alpha executive and kernel modes definitions.
Optimize PowerPC case, precomputing mmu_idx when MSR register changes
  and using the same definition in code translation code.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3384 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-10-14 07:07:08 +00:00
j_mayer c732abe222 Unify '-cpu ?' option. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3380 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-10-12 06:47:46 +00:00
ths 198a74de4c Move get_sp_from_cpustate from cpu.h to target_signal.h. 
Enable sigaltstack processing for more architectures.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3253 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-09-27 16:44:32 +00:00
ths a04e134ad1 linux-user sigaltstack() syscall, by Thayne Harbaugh. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3252 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-09-27 13:57:58 +00:00
ths 387a8fe505 Optimise instructions accessing CP0, by Aurelien Jarno. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3235 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-09-25 14:49:47 +00:00
ths e189e74868 Per-CPU instruction decoding implementation, by Aurelien Jarno. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3228 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-09-24 12:48:00 +00:00
ths ead9360e2f Partial support for 34K multithreading, not functional yet. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3156 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-09-06 00:18:15 +00:00
ths e034e2c39a Handle MIPS64 SEGBITS value correctly. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3011 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-06-23 18:04:12 +00:00
ths 9467d44c4d Move target-specific defines to the target directories. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2940 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-06-03 21:02:38 +00:00
ths 33ac7f1630 Don't kill the registered irqs on reset. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2903 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-05-31 16:18:58 +00:00
ths 51b2772f28 Fix CPU (re-)selection on reset. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2900 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-05-30 20:46:02 +00:00
ths 78749ba859 Fix usermode check, thanks Aurelien Jarno. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2897 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-05-29 18:55:34 +00:00
ths 5e755519ac Don't check the FPU state for each FPU instruction, use hflags to 
handle this per-tb.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2896 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-05-29 16:52:57 +00:00
ths 6e473128b6 Handle PX/UX status flags correctly, by Aurelien Jarno. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2892 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-05-28 20:36:48 +00:00
ths fd88b6abab The 24k wants more watch and srsmap registers. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2849 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-05-23 08:24:25 +00:00
ths fd4a04ebb2 - Move FPU exception handling into helper functions, since they are big. 
- Fix FP-conditional branches.
- Check FPU register mode at runtime, not translation time, as the F64
  status bit can change.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2828 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-05-18 11:55:54 +00:00
ths 388bb21af6 MIPS linux-user update. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2810 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-05-13 13:58:00 +00:00
ths 29929e3490 MIPS TLB style selection at runtime, by Herve Poussineau. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2809 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-05-13 13:49:44 +00:00
ths 5a5012ecbd MIPS 64-bit FPU support, plus some collateral bugfixes in the 
conditional branch handling.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2779 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-05-07 13:55:33 +00:00
ths fcb4a419f5 Choose number of TLBs at runtime, by Herve Poussineau. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2693 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-04-17 15:26:47 +00:00
pbrook d537cf6c86 Unify IRQ handling. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2635 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-04-07 18:14:41 +00:00