mirror of https://github.com/proxmox/mirror_qemu
294 lines
9.1 KiB
C
294 lines
9.1 KiB
C
/*
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* Decode table flags, mostly based on Intel SDM.
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*
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* Copyright (c) 2022 Red Hat, Inc.
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*
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* Author: Paolo Bonzini <pbonzini@redhat.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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typedef enum X86OpType {
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X86_TYPE_None,
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X86_TYPE_A, /* Implicit */
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X86_TYPE_B, /* VEX.vvvv selects a GPR */
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X86_TYPE_C, /* REG in the modrm byte selects a control register */
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X86_TYPE_D, /* REG in the modrm byte selects a debug register */
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X86_TYPE_E, /* ALU modrm operand */
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X86_TYPE_F, /* EFLAGS/RFLAGS */
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X86_TYPE_G, /* REG in the modrm byte selects a GPR */
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X86_TYPE_H, /* For AVX, VEX.vvvv selects an XMM/YMM register */
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X86_TYPE_I, /* Immediate */
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X86_TYPE_J, /* Relative offset for a jump */
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X86_TYPE_L, /* The upper 4 bits of the immediate select a 128-bit register */
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X86_TYPE_M, /* modrm byte selects a memory operand */
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X86_TYPE_N, /* R/M in the modrm byte selects an MMX register */
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X86_TYPE_O, /* Absolute address encoded in the instruction */
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X86_TYPE_P, /* reg in the modrm byte selects an MMX register */
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X86_TYPE_Q, /* MMX modrm operand */
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X86_TYPE_R, /* R/M in the modrm byte selects a register */
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X86_TYPE_S, /* reg selects a segment register */
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X86_TYPE_U, /* R/M in the modrm byte selects an XMM/YMM register */
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X86_TYPE_V, /* reg in the modrm byte selects an XMM/YMM register */
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X86_TYPE_W, /* XMM/YMM modrm operand */
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X86_TYPE_X, /* string source */
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X86_TYPE_Y, /* string destination */
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/* Custom */
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X86_TYPE_WM, /* modrm byte selects an XMM/YMM memory operand */
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X86_TYPE_2op, /* 2-operand RMW instruction */
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X86_TYPE_LoBits, /* encoded in bits 0-2 of the operand + REX.B */
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X86_TYPE_0, /* Hard-coded GPRs (RAX..RDI) */
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X86_TYPE_1,
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X86_TYPE_2,
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X86_TYPE_3,
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X86_TYPE_4,
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X86_TYPE_5,
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X86_TYPE_6,
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X86_TYPE_7,
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X86_TYPE_ES, /* Hard-coded segment registers */
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X86_TYPE_CS,
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X86_TYPE_SS,
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X86_TYPE_DS,
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X86_TYPE_FS,
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X86_TYPE_GS,
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} X86OpType;
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typedef enum X86OpSize {
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X86_SIZE_None,
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X86_SIZE_a, /* BOUND operand */
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X86_SIZE_b, /* byte */
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X86_SIZE_d, /* 32-bit */
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X86_SIZE_dq, /* SSE/AVX 128-bit */
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X86_SIZE_p, /* Far pointer */
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X86_SIZE_pd, /* SSE/AVX packed double precision */
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X86_SIZE_pi, /* MMX */
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X86_SIZE_ps, /* SSE/AVX packed single precision */
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X86_SIZE_q, /* 64-bit */
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X86_SIZE_qq, /* AVX 256-bit */
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X86_SIZE_s, /* Descriptor */
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X86_SIZE_sd, /* SSE/AVX scalar double precision */
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X86_SIZE_ss, /* SSE/AVX scalar single precision */
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X86_SIZE_si, /* 32-bit GPR */
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X86_SIZE_v, /* 16/32/64-bit, based on operand size */
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X86_SIZE_w, /* 16-bit */
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X86_SIZE_x, /* 128/256-bit, based on operand size */
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X86_SIZE_y, /* 32/64-bit, based on operand size */
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X86_SIZE_z, /* 16-bit for 16-bit operand size, else 32-bit */
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/* Custom */
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X86_SIZE_d64,
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X86_SIZE_f64,
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X86_SIZE_xh, /* SSE/AVX packed half register */
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} X86OpSize;
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typedef enum X86CPUIDFeature {
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X86_FEAT_None,
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X86_FEAT_3DNOW,
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X86_FEAT_ADX,
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X86_FEAT_AES,
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X86_FEAT_AVX,
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X86_FEAT_AVX2,
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X86_FEAT_BMI1,
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X86_FEAT_BMI2,
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X86_FEAT_CMPCCXADD,
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X86_FEAT_F16C,
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X86_FEAT_FMA,
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X86_FEAT_MOVBE,
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X86_FEAT_PCLMULQDQ,
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X86_FEAT_SHA_NI,
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X86_FEAT_SSE,
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X86_FEAT_SSE2,
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X86_FEAT_SSE3,
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X86_FEAT_SSSE3,
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X86_FEAT_SSE41,
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X86_FEAT_SSE42,
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X86_FEAT_SSE4A,
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} X86CPUIDFeature;
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/* Execution flags */
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typedef enum X86OpUnit {
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X86_OP_SKIP, /* not valid or managed by emission function */
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X86_OP_SEG, /* segment selector */
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X86_OP_CR, /* control register */
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X86_OP_DR, /* debug register */
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X86_OP_INT, /* loaded into/stored from s->T0/T1 */
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X86_OP_IMM, /* immediate */
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X86_OP_SSE, /* address in either s->ptrX or s->A0 depending on has_ea */
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X86_OP_MMX, /* address in either s->ptrX or s->A0 depending on has_ea */
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} X86OpUnit;
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typedef enum X86InsnCheck {
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/* Illegal or exclusive to 64-bit mode */
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X86_CHECK_i64 = 1,
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X86_CHECK_o64 = 2,
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/* Fault outside protected mode */
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X86_CHECK_prot = 4,
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/* Privileged instruction checks */
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X86_CHECK_cpl0 = 8,
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X86_CHECK_vm86_iopl = 16,
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X86_CHECK_cpl_iopl = 32,
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X86_CHECK_iopl = X86_CHECK_cpl_iopl | X86_CHECK_vm86_iopl,
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/* Fault if VEX.L=1 */
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X86_CHECK_VEX128 = 64,
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/* Fault if VEX.W=1 */
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X86_CHECK_W0 = 128,
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/* Fault if VEX.W=0 */
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X86_CHECK_W1 = 256,
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} X86InsnCheck;
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typedef enum X86InsnSpecial {
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X86_SPECIAL_None,
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/* Accepts LOCK prefix; LOCKed operations do not load or writeback operand 0 */
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X86_SPECIAL_HasLock,
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/* Always locked if it has a memory operand (XCHG) */
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X86_SPECIAL_Locked,
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/*
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* Rd/Mb or Rd/Mw in the manual: register operand 0 is treated as 32 bits
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* (and writeback zero-extends it to 64 bits if applicable). PREFIX_DATA
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* does not trigger 16-bit writeback and, as a side effect, high-byte
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* registers are never used.
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*/
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X86_SPECIAL_Op0_Rd,
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/*
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* Ry/Mb in the manual (PINSRB). However, the high bits are never used by
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* the instruction in either the register or memory cases; the *real* effect
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* of this modifier is that high-byte registers are never used, even without
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* a REX prefix. Therefore, PINSRW does not need it despite having Ry/Mw.
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*/
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X86_SPECIAL_Op2_Ry,
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/*
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* Register operand 2 is extended to full width, while a memory operand
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* is doubled in size if VEX.L=1.
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*/
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X86_SPECIAL_AVXExtMov,
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/*
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* MMX instruction exists with no prefix; if there is no prefix, V/H/W/U operands
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* become P/P/Q/N, and size "x" becomes "q".
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*/
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X86_SPECIAL_MMX,
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/* When loaded into s->T0, register operand 1 is zero/sign extended. */
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X86_SPECIAL_SExtT0,
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X86_SPECIAL_ZExtT0,
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} X86InsnSpecial;
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/*
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* Special cases for instructions that operate on XMM/YMM registers. Intel
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* retconned all of them to have VEX exception classes other than 0 and 13, so
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* all these only matter for instructions that have a VEX exception class.
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* Based on tables in the "AVX and SSE Instruction Exception Specification"
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* section of the manual.
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*/
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typedef enum X86VEXSpecial {
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/* Legacy SSE instructions that allow unaligned operands */
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X86_VEX_SSEUnaligned,
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/*
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* Used for instructions that distinguish the XMM operand type with an
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* instruction prefix; legacy SSE encodings will allow unaligned operands
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* for scalar operands only (identified by a REP prefix). In this case,
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* the decoding table uses "x" for the vector operands instead of specifying
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* pd/ps/sd/ss individually.
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*/
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X86_VEX_REPScalar,
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/*
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* VEX instructions that only support 256-bit operands with AVX2 (Table 2-17
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* column 3). Columns 2 and 4 (instructions limited to 256- and 127-bit
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* operands respectively) are implicit in the presence of dq and qq
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* operands, and thus handled by decode_op_size.
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*/
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X86_VEX_AVX2_256,
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} X86VEXSpecial;
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typedef struct X86OpEntry X86OpEntry;
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typedef struct X86DecodedInsn X86DecodedInsn;
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/* Decode function for multibyte opcodes. */
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typedef void (*X86DecodeFunc)(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b);
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/* Code generation function. */
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typedef void (*X86GenFunc)(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode);
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struct X86OpEntry {
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/* Based on the is_decode flags. */
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union {
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X86GenFunc gen;
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X86DecodeFunc decode;
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};
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/* op0 is always written, op1 and op2 are always read. */
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X86OpType op0:8;
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X86OpSize s0:8;
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X86OpType op1:8;
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X86OpSize s1:8;
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X86OpType op2:8;
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X86OpSize s2:8;
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/* Must be I and b respectively if present. */
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X86OpType op3:8;
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X86OpSize s3:8;
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X86InsnSpecial special:8;
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X86CPUIDFeature cpuid:8;
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unsigned vex_class:8;
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X86VEXSpecial vex_special:8;
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unsigned valid_prefix:16;
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unsigned check:16;
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unsigned intercept:8;
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bool is_decode:1;
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};
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typedef struct X86DecodedOp {
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int8_t n;
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MemOp ot; /* For b/c/d/p/s/q/v/w/y/z */
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X86OpUnit unit;
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bool has_ea;
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int offset; /* For MMX and SSE */
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/*
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* This field is used internally by macros OP0_PTR/OP1_PTR/OP2_PTR,
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* do not access directly!
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*/
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TCGv_ptr v_ptr;
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} X86DecodedOp;
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struct X86DecodedInsn {
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X86OpEntry e;
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X86DecodedOp op[3];
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target_ulong immediate;
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AddressParts mem;
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TCGv cc_dst, cc_src, cc_src2;
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TCGv_i32 cc_op_dynamic;
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int8_t cc_op;
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uint8_t b;
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};
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