mirror of https://github.com/proxmox/mirror_qemu
193 lines
5.8 KiB
C
193 lines
5.8 KiB
C
/*
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* pcie_host.c
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* utility functions for pci express host bridge.
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*
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* Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
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* VA Linux Systems Japan K.K.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#include "hw.h"
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#include "pci.h"
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#include "pcie_host.h"
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/*
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* PCI express mmcfig address
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* bit 20 - 28: bus number
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* bit 15 - 19: device number
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* bit 12 - 14: function number
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* bit 0 - 11: offset in configuration space of a given device
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*/
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#define PCIE_MMCFG_SIZE_MAX (1ULL << 28)
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#define PCIE_MMCFG_SIZE_MIN (1ULL << 20)
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#define PCIE_MMCFG_BUS_BIT 20
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#define PCIE_MMCFG_BUS_MASK 0x1ff
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#define PCIE_MMCFG_DEVFN_BIT 12
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#define PCIE_MMCFG_DEVFN_MASK 0xff
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#define PCIE_MMCFG_CONFOFFSET_MASK 0xfff
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#define PCIE_MMCFG_BUS(addr) (((addr) >> PCIE_MMCFG_BUS_BIT) & \
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PCIE_MMCFG_BUS_MASK)
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#define PCIE_MMCFG_DEVFN(addr) (((addr) >> PCIE_MMCFG_DEVFN_BIT) & \
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PCIE_MMCFG_DEVFN_MASK)
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#define PCIE_MMCFG_CONFOFFSET(addr) ((addr) & PCIE_MMCFG_CONFOFFSET_MASK)
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/* a helper function to get a PCIDevice for a given mmconfig address */
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static inline PCIDevice *pcie_mmcfg_addr_to_dev(PCIBus *s, uint32_t mmcfg_addr)
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{
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return pci_find_device(s, PCIE_MMCFG_BUS(mmcfg_addr),
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PCI_SLOT(PCIE_MMCFG_DEVFN(mmcfg_addr)),
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PCI_FUNC(PCIE_MMCFG_DEVFN(mmcfg_addr)));
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}
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static void pcie_mmcfg_data_write(PCIBus *s,
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uint32_t mmcfg_addr, uint32_t val, int len)
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{
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PCIDevice *pci_dev = pcie_mmcfg_addr_to_dev(s, mmcfg_addr);
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if (!pci_dev)
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return;
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pci_dev->config_write(pci_dev,
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PCIE_MMCFG_CONFOFFSET(mmcfg_addr), val, len);
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}
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static uint32_t pcie_mmcfg_data_read(PCIBus *s,
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uint32_t mmcfg_addr, int len)
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{
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PCIDevice *pci_dev = pcie_mmcfg_addr_to_dev(s, mmcfg_addr);
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uint32_t val;
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if (!pci_dev) {
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switch(len) {
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case 1:
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val = 0xff;
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break;
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case 2:
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val = 0xffff;
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break;
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default:
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case 4:
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val = 0xffffffff;
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break;
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}
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} else {
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val = pci_dev->config_read(pci_dev,
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PCIE_MMCFG_CONFOFFSET(mmcfg_addr), len);
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}
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return val;
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}
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static void pcie_mmcfg_data_writeb(void *opaque,
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target_phys_addr_t addr, uint32_t value)
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{
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PCIExpressHost *e = opaque;
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pcie_mmcfg_data_write(e->pci.bus, addr - e->base_addr, value, 1);
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}
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static void pcie_mmcfg_data_writew(void *opaque,
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target_phys_addr_t addr, uint32_t value)
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{
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PCIExpressHost *e = opaque;
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pcie_mmcfg_data_write(e->pci.bus, addr - e->base_addr, value, 2);
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}
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static void pcie_mmcfg_data_writel(void *opaque,
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target_phys_addr_t addr, uint32_t value)
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{
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PCIExpressHost *e = opaque;
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pcie_mmcfg_data_write(e->pci.bus, addr - e->base_addr, value, 4);
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}
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static uint32_t pcie_mmcfg_data_readb(void *opaque, target_phys_addr_t addr)
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{
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PCIExpressHost *e = opaque;
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return pcie_mmcfg_data_read(e->pci.bus, addr - e->base_addr, 1);
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}
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static uint32_t pcie_mmcfg_data_readw(void *opaque, target_phys_addr_t addr)
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{
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PCIExpressHost *e = opaque;
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return pcie_mmcfg_data_read(e->pci.bus, addr - e->base_addr, 2);
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}
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static uint32_t pcie_mmcfg_data_readl(void *opaque, target_phys_addr_t addr)
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{
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PCIExpressHost *e = opaque;
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return pcie_mmcfg_data_read(e->pci.bus, addr - e->base_addr, 4);
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}
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static CPUWriteMemoryFunc * const pcie_mmcfg_write[] =
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{
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pcie_mmcfg_data_writeb,
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pcie_mmcfg_data_writew,
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pcie_mmcfg_data_writel,
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};
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static CPUReadMemoryFunc * const pcie_mmcfg_read[] =
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{
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pcie_mmcfg_data_readb,
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pcie_mmcfg_data_readw,
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pcie_mmcfg_data_readl,
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};
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/* pcie_host::base_addr == PCIE_BASE_ADDR_UNMAPPED when it isn't mapped. */
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#define PCIE_BASE_ADDR_UNMAPPED ((target_phys_addr_t)-1ULL)
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int pcie_host_init(PCIExpressHost *e)
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{
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e->base_addr = PCIE_BASE_ADDR_UNMAPPED;
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e->mmio_index =
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cpu_register_io_memory(pcie_mmcfg_read, pcie_mmcfg_write, e);
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if (e->mmio_index < 0) {
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return -1;
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}
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return 0;
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}
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void pcie_host_mmcfg_unmap(PCIExpressHost *e)
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{
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if (e->base_addr != PCIE_BASE_ADDR_UNMAPPED) {
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cpu_register_physical_memory(e->base_addr, e->size, IO_MEM_UNASSIGNED);
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e->base_addr = PCIE_BASE_ADDR_UNMAPPED;
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}
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}
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void pcie_host_mmcfg_map(PCIExpressHost *e,
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target_phys_addr_t addr, uint32_t size)
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{
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assert(!(size & (size - 1))); /* power of 2 */
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assert(size >= PCIE_MMCFG_SIZE_MIN);
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assert(size <= PCIE_MMCFG_SIZE_MAX);
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e->base_addr = addr;
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e->size = size;
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cpu_register_physical_memory(e->base_addr, e->size, e->mmio_index);
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}
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void pcie_host_mmcfg_update(PCIExpressHost *e,
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int enable,
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target_phys_addr_t addr, uint32_t size)
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{
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pcie_host_mmcfg_unmap(e);
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if (enable) {
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pcie_host_mmcfg_map(e, addr, size);
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}
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}
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