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mirror_qemu/target/riscv
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Markus Armbruster a8b991b52d Clean up ill-advised or unusual header guards 
Leading underscores are ill-advised because such identifiers are
reserved.  Trailing underscores are merely ugly.  Strip both.

Our header guards commonly end in _H.  Normalize the exceptions.

Done with scripts/clean-header-guards.pl.

Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20190315145123.28030-7-armbru@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
[Changes to slirp/ dropped, as we're about to spin it off]
 		2019-05-13 08:58:55 +02:00
..
insn_trans decodetree: Add DisasContext argument to !function expanders 2019-05-06 11:18:34 -07:00
Makefile.objs target/riscv: Convert quadrant 0 of RVXC insns to decodetree 2019-03-13 10:34:06 +01:00
cpu.c qom/cpu: Simplify how CPUClass:cpu_dump_state() prints 2019-04-18 22:18:59 +02:00
cpu.h target: Simplify how the TARGET_cpu_list() print 2019-04-18 22:18:59 +02:00
cpu_bits.h RISC-V: Fixes to CSR_* register macros. 2019-03-19 05:13:24 -07:00
cpu_helper.c RISC-V: Update load reservation comment in do_interrupt 2019-03-19 05:14:40 -07:00
cpu_user.h RISC-V: linux-user support for RVE ABI 2019-03-19 05:14:39 -07:00
csr.c RISC-V: Add support for vectored interrupts 2019-03-19 05:14:39 -07:00
fpu_helper.c RISC-V: Use riscv prefix consistently on cpu helpers 2019-02-11 15:56:21 -08:00
gdbstub.c RISC-V: Add hooks to use the gdb xml files. 2019-03-19 05:13:24 -07:00
helper.h
…
insn16.decode target/riscv: Convert quadrant 2 of RVXC insns to decodetree 2019-03-13 10:40:46 +01:00
insn32-64.decode target/riscv: Convert RV64D insns to decodetree 2019-03-13 10:34:06 +01:00
insn32.decode target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists 2019-03-13 10:40:50 +01:00
instmap.h RISC-V TCG Code Generation 2018-03-07 08:30:28 +13:00
op_helper.c RISC-V: Use riscv prefix consistently on cpu helpers 2019-02-11 15:56:21 -08:00
pmp.c riscv: pmp: Log pmp access errors as guest errors 2019-03-19 05:14:38 -07:00
pmp.h Clean up ill-advised or unusual header guards 2019-05-13 08:58:55 +02:00
trace-events RISC-V: Convert trap debugging to trace events 2019-03-19 05:14:40 -07:00
translate.c decodetree: Add DisasContext argument to !function expanders 2019-05-06 11:18:34 -07:00