mirror of https://github.com/proxmox/mirror_qemu
175 lines
5.9 KiB
ReStructuredText
175 lines
5.9 KiB
ReStructuredText
XIVE for sPAPR (pseries machines)
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=================================
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The POWER9 processor comes with a new interrupt controller
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architecture, called XIVE as "eXternal Interrupt Virtualization
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Engine". It supports a larger number of interrupt sources and offers
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virtualization features which enables the HW to deliver interrupts
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directly to virtual processors without hypervisor assistance.
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A QEMU ``pseries`` machine (which is PAPR compliant) using POWER9
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processors can run under two interrupt modes:
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- *Legacy Compatibility Mode*
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the hypervisor provides identical interfaces and similar
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functionality to PAPR+ Version 2.7. This is the default mode
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It is also referred as *XICS* in QEMU.
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- *XIVE native exploitation mode*
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the hypervisor provides new interfaces to manage the XIVE control
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structures, and provides direct control for interrupt management
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through MMIO pages.
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Which interrupt modes can be used by the machine is negotiated with
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the guest O/S during the Client Architecture Support negotiation
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sequence. The two modes are mutually exclusive.
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Both interrupt mode share the same IRQ number space. See below for the
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layout.
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CAS Negotiation
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---------------
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QEMU advertises the supported interrupt modes in the device tree
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property "ibm,arch-vec-5-platform-support" in byte 23 and the OS
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Selection for XIVE is indicated in the "ibm,architecture-vec-5"
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property byte 23.
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The interrupt modes supported by the machine depend on the CPU type
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(POWER9 is required for XIVE) but also on the machine property
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``ic-mode`` which can be set on the command line. It can take the
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following values: ``xics``, ``xive``, ``dual`` and currently ``xics``
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is the default but it may change in the future.
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The choosen interrupt mode is activated after a reconfiguration done
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in a machine reset.
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XIVE Device tree properties
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---------------------------
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The properties for the PAPR interrupt controller node when the *XIVE
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native exploitation mode* is selected shoud contain:
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- ``device_type``
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value should be "power-ivpe".
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- ``compatible``
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value should be "ibm,power-ivpe".
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- ``reg``
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contains the base address and size of the thread interrupt
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managnement areas (TIMA), for the User level and for the Guest OS
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level. Only the Guest OS level is taken into account today.
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- ``ibm,xive-eq-sizes``
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the size of the event queues. One cell per size supported, contains
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log2 of size, in ascending order.
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- ``ibm,xive-lisn-ranges``
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the IRQ interrupt number ranges assigned to the guest for the IPIs.
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The root node also exports :
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- ``ibm,plat-res-int-priorities``
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contains a list of priorities that the hypervisor has reserved for
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its own use.
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IRQ number space
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----------------
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IRQ Number space of the ``pseries`` machine is 8K wide and is the same
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for both interrupt mode. The different ranges are defined as follow :
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- ``0x0000 .. 0x0FFF`` 4K CPU IPIs (only used under XIVE)
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- ``0x1000 .. 0x1000`` 1 EPOW
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- ``0x1001 .. 0x1001`` 1 HOTPLUG
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- ``0x1100 .. 0x11FF`` 256 VIO devices
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- ``0x1200 .. 0x127F`` 32 PHBs devices
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- ``0x1280 .. 0x12FF`` unused
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- ``0x1300 .. 0x1FFF`` PHB MSIs
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Monitoring XIVE
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---------------
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The state of the XIVE interrupt controller can be queried through the
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monitor commands ``info pic``. The output comes in two parts.
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First, the state of the thread interrupt context registers is dumped
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for each CPU :
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::
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(qemu) info pic
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CPU[0000]: QW NSR CPPR IPB LSMFB ACK# INC AGE PIPR W2
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CPU[0000]: USER 00 00 00 00 00 00 00 00 00000000
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CPU[0000]: OS 00 ff 00 00 ff 00 ff ff 80000400
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CPU[0000]: POOL 00 00 00 00 00 00 00 00 00000000
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CPU[0000]: PHYS 00 00 00 00 00 00 00 ff 00000000
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...
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In the case of a ``pseries`` machine, QEMU acts as the hypervisor and only
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the O/S and USER register rings make sense. ``W2`` contains the vCPU CAM
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line which is set to the VP identifier.
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Then comes the routing information which aggregates the EAS and the
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END configuration:
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::
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...
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LISN PQ EISN CPU/PRIO EQ
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00000000 MSI -- 00000010 0/6 380/16384 @1fe3e0000 ^1 [ 80000010 ... ]
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00000001 MSI -- 00000010 1/6 305/16384 @1fc230000 ^1 [ 80000010 ... ]
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00000002 MSI -- 00000010 2/6 220/16384 @1fc2f0000 ^1 [ 80000010 ... ]
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00000003 MSI -- 00000010 3/6 201/16384 @1fc390000 ^1 [ 80000010 ... ]
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00000004 MSI -Q M 00000000
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00000005 MSI -Q M 00000000
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00000006 MSI -Q M 00000000
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00000007 MSI -Q M 00000000
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00001000 MSI -- 00000012 0/6 380/16384 @1fe3e0000 ^1 [ 80000010 ... ]
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00001001 MSI -- 00000013 0/6 380/16384 @1fe3e0000 ^1 [ 80000010 ... ]
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00001100 MSI -- 00000100 1/6 305/16384 @1fc230000 ^1 [ 80000010 ... ]
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00001101 MSI -Q M 00000000
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00001200 LSI -Q M 00000000
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00001201 LSI -Q M 00000000
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00001202 LSI -Q M 00000000
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00001203 LSI -Q M 00000000
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00001300 MSI -- 00000102 1/6 305/16384 @1fc230000 ^1 [ 80000010 ... ]
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00001301 MSI -- 00000103 2/6 220/16384 @1fc2f0000 ^1 [ 80000010 ... ]
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00001302 MSI -- 00000104 3/6 201/16384 @1fc390000 ^1 [ 80000010 ... ]
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The source information and configuration:
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- The ``LISN`` column outputs the interrupt number of the source in
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range ``[ 0x0 ... 0x1FFF ]`` and its type : ``MSI`` or ``LSI``
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- The ``PQ`` column reflects the state of the PQ bits of the source :
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- ``--`` source is ready to take events
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- ``P-`` an event was sent and an EOI is PENDING
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- ``PQ`` an event was QUEUED
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- ``-Q`` source is OFF
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a ``M`` indicates that source is *MASKED* at the EAS level,
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The targeting configuration :
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- The ``EISN`` column is the event data that will be queued in the event
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queue of the O/S.
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- The ``CPU/PRIO`` column is the tuple defining the CPU number and
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priority queue serving the source.
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- The ``EQ`` column outputs :
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- the current index of the event queue/ the max number of entries
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- the O/S event queue address
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- the toggle bit
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- the last entries that were pushed in the event queue.
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