mirror of https://github.com/proxmox/mirror_qemu
32bd322a01
The armv7m systick timer is a 24-bit decrementing, wrap-on-zero, clear-on-write counter. Our current implementation has various bugs and dubious workarounds in it (for instance see https://bugs.launchpad.net/qemu/+bug/1872237). We have an implementation of a simple decrementing counter and we put a lot of effort into making sure it handles the interesting corner cases (like "spend a cycle at 0 before reloading") -- ptimer. Rewrite the systick timer to use a ptimer rather than a raw QEMU timer. Unfortunately this is a migration compatibility break, which will affect all M-profile boards. Among other bugs, this fixes https://bugs.launchpad.net/qemu/+bug/1872237 : now writes to SYST_CVR when the timer is enabled correctly do nothing; when the timer is enabled via SYST_CSR.ENABLE, the ptimer code will (because of POLICY_NO_IMMEDIATE_RELOAD) arrange that after one timer tick the counter is reloaded from SYST_RVR and then counts down from there, as the architecture requires. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20201015151829.14656-3-peter.maydell@linaro.org |
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| .. | ||
| a9gtimer.h | ||
| allwinner-a10-pit.h | ||
| arm_mptimer.h | ||
| armv7m_systick.h | ||
| aspeed_timer.h | ||
| avr_timer16.h | ||
| bcm2835_systmr.h | ||
| cmsdk-apb-dualtimer.h | ||
| cmsdk-apb-timer.h | ||
| digic-timer.h | ||
| hpet.h | ||
| i8254.h | ||
| i8254_internal.h | ||
| imx_epit.h | ||
| imx_gpt.h | ||
| mips_gictimer.h | ||
| mss-timer.h | ||
| npcm7xx_timer.h | ||
| nrf51_timer.h | ||
| renesas_cmt.h | ||
| renesas_tmr.h | ||
| stm32f2xx_timer.h | ||
| tmu012.h | ||