mirror of https://github.com/proxmox/mirror_qemu
130 lines
3.7 KiB
C
130 lines
3.7 KiB
C
/*
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* QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
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*
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* PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
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*
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* Copyright (c) 2010,2011 David Gibson, IBM Corporation.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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*/
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#if !defined(__XICS_H__)
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#define __XICS_H__
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#include "hw/sysbus.h"
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#define TYPE_XICS "xics"
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#define XICS(obj) OBJECT_CHECK(XICSState, (obj), TYPE_XICS)
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#define XICS_IPI 0x2
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#define XICS_BUID 0x1
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#define XICS_IRQ_BASE (XICS_BUID << 12)
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/*
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* We currently only support one BUID which is our interrupt base
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* (the kernel implementation supports more but we don't exploit
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* that yet)
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*/
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typedef struct XICSState XICSState;
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typedef struct ICPStateClass ICPStateClass;
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typedef struct ICPState ICPState;
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typedef struct ICSStateClass ICSStateClass;
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typedef struct ICSState ICSState;
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typedef struct ICSIRQState ICSIRQState;
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struct XICSState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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uint32_t nr_servers;
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uint32_t nr_irqs;
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ICPState *ss;
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ICSState *ics;
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};
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#define TYPE_ICP "icp"
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#define ICP(obj) OBJECT_CHECK(ICPState, (obj), TYPE_ICP)
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#define ICP_CLASS(klass) \
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OBJECT_CLASS_CHECK(ICPStateClass, (klass), TYPE_ICP)
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#define ICP_GET_CLASS(obj) \
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OBJECT_GET_CLASS(ICPStateClass, (obj), TYPE_ICP)
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struct ICPStateClass {
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DeviceClass parent_class;
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void (*pre_save)(ICPState *s);
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int (*post_load)(ICPState *s, int version_id);
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};
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struct ICPState {
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/*< private >*/
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DeviceState parent_obj;
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/*< public >*/
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uint32_t xirr;
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uint8_t pending_priority;
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uint8_t mfrr;
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qemu_irq output;
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};
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#define TYPE_ICS "ics"
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#define ICS(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS)
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#define ICS_CLASS(klass) \
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OBJECT_CLASS_CHECK(ICSStateClass, (klass), TYPE_ICS)
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#define ICS_GET_CLASS(obj) \
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OBJECT_GET_CLASS(ICSStateClass, (obj), TYPE_ICS)
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struct ICSStateClass {
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DeviceClass parent_class;
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void (*pre_save)(ICSState *s);
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int (*post_load)(ICSState *s, int version_id);
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};
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struct ICSState {
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/*< private >*/
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DeviceState parent_obj;
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/*< public >*/
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uint32_t nr_irqs;
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uint32_t offset;
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qemu_irq *qirqs;
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bool *islsi;
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ICSIRQState *irqs;
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XICSState *icp;
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};
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struct ICSIRQState {
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uint32_t server;
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uint8_t priority;
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uint8_t saved_priority;
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#define XICS_STATUS_ASSERTED 0x1
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#define XICS_STATUS_SENT 0x2
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#define XICS_STATUS_REJECTED 0x4
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#define XICS_STATUS_MASKED_PENDING 0x8
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uint8_t status;
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};
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qemu_irq xics_get_qirq(XICSState *icp, int irq);
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void xics_set_irq_type(XICSState *icp, int irq, bool lsi);
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void xics_cpu_setup(XICSState *icp, PowerPCCPU *cpu);
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#endif /* __XICS_H__ */
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