mirror of https://github.com/proxmox/mirror_qemu
902 lines
26 KiB
C
902 lines
26 KiB
C
/*
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* QEMU 16550A UART emulation
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*
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* Copyright (c) 2003-2004 Fabrice Bellard
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* Copyright (c) 2008 Citrix Systems, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h"
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#include "qemu-char.h"
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#include "isa.h"
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#include "pc.h"
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#include "qemu-timer.h"
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//#define DEBUG_SERIAL
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#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
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#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
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#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
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#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
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#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
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#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
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#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
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#define UART_IIR_MSI 0x00 /* Modem status interrupt */
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#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
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#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
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#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
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#define UART_IIR_CTI 0x0C /* Character Timeout Indication */
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#define UART_IIR_FENF 0x80 /* Fifo enabled, but not functionning */
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#define UART_IIR_FE 0xC0 /* Fifo enabled */
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/*
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* These are the definitions for the Modem Control Register
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*/
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#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
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#define UART_MCR_OUT2 0x08 /* Out2 complement */
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#define UART_MCR_OUT1 0x04 /* Out1 complement */
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#define UART_MCR_RTS 0x02 /* RTS complement */
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#define UART_MCR_DTR 0x01 /* DTR complement */
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/*
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* These are the definitions for the Modem Status Register
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*/
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#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
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#define UART_MSR_RI 0x40 /* Ring Indicator */
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#define UART_MSR_DSR 0x20 /* Data Set Ready */
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#define UART_MSR_CTS 0x10 /* Clear to Send */
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#define UART_MSR_DDCD 0x08 /* Delta DCD */
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#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
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#define UART_MSR_DDSR 0x02 /* Delta DSR */
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#define UART_MSR_DCTS 0x01 /* Delta CTS */
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#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
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#define UART_LSR_TEMT 0x40 /* Transmitter empty */
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#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
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#define UART_LSR_BI 0x10 /* Break interrupt indicator */
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#define UART_LSR_FE 0x08 /* Frame error indicator */
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#define UART_LSR_PE 0x04 /* Parity error indicator */
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#define UART_LSR_OE 0x02 /* Overrun error indicator */
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#define UART_LSR_DR 0x01 /* Receiver data ready */
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#define UART_LSR_INT_ANY 0x1E /* Any of the lsr-interrupt-triggering status bits */
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/* Interrupt trigger levels. The byte-counts are for 16550A - in newer UARTs the byte-count for each ITL is higher. */
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#define UART_FCR_ITL_1 0x00 /* 1 byte ITL */
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#define UART_FCR_ITL_2 0x40 /* 4 bytes ITL */
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#define UART_FCR_ITL_3 0x80 /* 8 bytes ITL */
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#define UART_FCR_ITL_4 0xC0 /* 14 bytes ITL */
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#define UART_FCR_DMS 0x08 /* DMA Mode Select */
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#define UART_FCR_XFR 0x04 /* XMIT Fifo Reset */
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#define UART_FCR_RFR 0x02 /* RCVR Fifo Reset */
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#define UART_FCR_FE 0x01 /* FIFO Enable */
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#define UART_FIFO_LENGTH 16 /* 16550A Fifo Length */
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#define XMIT_FIFO 0
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#define RECV_FIFO 1
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#define MAX_XMIT_RETRY 4
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typedef struct SerialFIFO {
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uint8_t data[UART_FIFO_LENGTH];
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uint8_t count;
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uint8_t itl; /* Interrupt Trigger Level */
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uint8_t tail;
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uint8_t head;
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} SerialFIFO;
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struct SerialState {
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uint16_t divider;
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uint8_t rbr; /* receive register */
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uint8_t thr; /* transmit holding register */
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uint8_t tsr; /* transmit shift register */
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uint8_t ier;
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uint8_t iir; /* read only */
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uint8_t lcr;
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uint8_t mcr;
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uint8_t lsr; /* read only */
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uint8_t msr; /* read only */
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uint8_t scr;
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uint8_t fcr;
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uint8_t fcr_vmstate; /* we can't write directly this value
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it has side effects */
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/* NOTE: this hidden state is necessary for tx irq generation as
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it can be reset while reading iir */
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int thr_ipending;
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qemu_irq irq;
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CharDriverState *chr;
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int last_break_enable;
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int it_shift;
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int baudbase;
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int tsr_retry;
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uint64_t last_xmit_ts; /* Time when the last byte was successfully sent out of the tsr */
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SerialFIFO recv_fifo;
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SerialFIFO xmit_fifo;
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struct QEMUTimer *fifo_timeout_timer;
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int timeout_ipending; /* timeout interrupt pending state */
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struct QEMUTimer *transmit_timer;
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uint64_t char_transmit_time; /* time to transmit a char in ticks*/
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int poll_msl;
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struct QEMUTimer *modem_status_poll;
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};
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typedef struct ISASerialState {
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ISADevice dev;
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uint32_t iobase;
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uint32_t isairq;
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SerialState state;
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} ISASerialState;
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static void serial_receive1(void *opaque, const uint8_t *buf, int size);
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static void fifo_clear(SerialState *s, int fifo)
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{
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SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo;
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memset(f->data, 0, UART_FIFO_LENGTH);
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f->count = 0;
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f->head = 0;
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f->tail = 0;
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}
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static int fifo_put(SerialState *s, int fifo, uint8_t chr)
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{
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SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo;
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f->data[f->head++] = chr;
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if (f->head == UART_FIFO_LENGTH)
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f->head = 0;
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f->count++;
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return 1;
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}
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static uint8_t fifo_get(SerialState *s, int fifo)
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{
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SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo;
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uint8_t c;
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if(f->count == 0)
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return 0;
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c = f->data[f->tail++];
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if (f->tail == UART_FIFO_LENGTH)
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f->tail = 0;
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f->count--;
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return c;
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}
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static void serial_update_irq(SerialState *s)
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{
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uint8_t tmp_iir = UART_IIR_NO_INT;
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if ((s->ier & UART_IER_RLSI) && (s->lsr & UART_LSR_INT_ANY)) {
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tmp_iir = UART_IIR_RLSI;
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} else if ((s->ier & UART_IER_RDI) && s->timeout_ipending) {
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/* Note that(s->ier & UART_IER_RDI) can mask this interrupt,
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* this is not in the specification but is observed on existing
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* hardware. */
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tmp_iir = UART_IIR_CTI;
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} else if ((s->ier & UART_IER_RDI) && (s->lsr & UART_LSR_DR) &&
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(!(s->fcr & UART_FCR_FE) ||
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s->recv_fifo.count >= s->recv_fifo.itl)) {
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tmp_iir = UART_IIR_RDI;
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} else if ((s->ier & UART_IER_THRI) && s->thr_ipending) {
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tmp_iir = UART_IIR_THRI;
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} else if ((s->ier & UART_IER_MSI) && (s->msr & UART_MSR_ANY_DELTA)) {
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tmp_iir = UART_IIR_MSI;
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}
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s->iir = tmp_iir | (s->iir & 0xF0);
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if (tmp_iir != UART_IIR_NO_INT) {
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qemu_irq_raise(s->irq);
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} else {
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qemu_irq_lower(s->irq);
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}
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}
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static void serial_update_parameters(SerialState *s)
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{
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int speed, parity, data_bits, stop_bits, frame_size;
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QEMUSerialSetParams ssp;
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if (s->divider == 0)
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return;
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frame_size = 1;
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if (s->lcr & 0x08) {
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if (s->lcr & 0x10)
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parity = 'E';
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else
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parity = 'O';
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} else {
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parity = 'N';
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frame_size = 0;
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}
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if (s->lcr & 0x04)
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stop_bits = 2;
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else
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stop_bits = 1;
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data_bits = (s->lcr & 0x03) + 5;
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frame_size += data_bits + stop_bits;
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speed = s->baudbase / s->divider;
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ssp.speed = speed;
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ssp.parity = parity;
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ssp.data_bits = data_bits;
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ssp.stop_bits = stop_bits;
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s->char_transmit_time = (get_ticks_per_sec() / speed) * frame_size;
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qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
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#if 0
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printf("speed=%d parity=%c data=%d stop=%d\n",
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speed, parity, data_bits, stop_bits);
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#endif
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}
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static void serial_update_msl(SerialState *s)
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{
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uint8_t omsr;
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int flags;
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qemu_del_timer(s->modem_status_poll);
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if (qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags) == -ENOTSUP) {
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s->poll_msl = -1;
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return;
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}
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omsr = s->msr;
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s->msr = (flags & CHR_TIOCM_CTS) ? s->msr | UART_MSR_CTS : s->msr & ~UART_MSR_CTS;
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s->msr = (flags & CHR_TIOCM_DSR) ? s->msr | UART_MSR_DSR : s->msr & ~UART_MSR_DSR;
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s->msr = (flags & CHR_TIOCM_CAR) ? s->msr | UART_MSR_DCD : s->msr & ~UART_MSR_DCD;
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s->msr = (flags & CHR_TIOCM_RI) ? s->msr | UART_MSR_RI : s->msr & ~UART_MSR_RI;
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if (s->msr != omsr) {
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/* Set delta bits */
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s->msr = s->msr | ((s->msr >> 4) ^ (omsr >> 4));
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/* UART_MSR_TERI only if change was from 1 -> 0 */
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if ((s->msr & UART_MSR_TERI) && !(omsr & UART_MSR_RI))
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s->msr &= ~UART_MSR_TERI;
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serial_update_irq(s);
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}
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/* The real 16550A apparently has a 250ns response latency to line status changes.
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We'll be lazy and poll only every 10ms, and only poll it at all if MSI interrupts are turned on */
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if (s->poll_msl)
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qemu_mod_timer(s->modem_status_poll, qemu_get_clock(vm_clock) + get_ticks_per_sec() / 100);
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}
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static void serial_xmit(void *opaque)
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{
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SerialState *s = opaque;
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uint64_t new_xmit_ts = qemu_get_clock(vm_clock);
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if (s->tsr_retry <= 0) {
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if (s->fcr & UART_FCR_FE) {
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s->tsr = fifo_get(s,XMIT_FIFO);
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if (!s->xmit_fifo.count)
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s->lsr |= UART_LSR_THRE;
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} else {
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s->tsr = s->thr;
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s->lsr |= UART_LSR_THRE;
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}
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}
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if (s->mcr & UART_MCR_LOOP) {
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/* in loopback mode, say that we just received a char */
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serial_receive1(s, &s->tsr, 1);
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} else if (qemu_chr_write(s->chr, &s->tsr, 1) != 1) {
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if ((s->tsr_retry > 0) && (s->tsr_retry <= MAX_XMIT_RETRY)) {
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s->tsr_retry++;
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qemu_mod_timer(s->transmit_timer, new_xmit_ts + s->char_transmit_time);
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return;
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} else if (s->poll_msl < 0) {
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/* If we exceed MAX_XMIT_RETRY and the backend is not a real serial port, then
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drop any further failed writes instantly, until we get one that goes through.
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This is to prevent guests that log to unconnected pipes or pty's from stalling. */
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s->tsr_retry = -1;
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}
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}
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else {
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s->tsr_retry = 0;
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}
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s->last_xmit_ts = qemu_get_clock(vm_clock);
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if (!(s->lsr & UART_LSR_THRE))
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qemu_mod_timer(s->transmit_timer, s->last_xmit_ts + s->char_transmit_time);
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if (s->lsr & UART_LSR_THRE) {
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s->lsr |= UART_LSR_TEMT;
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s->thr_ipending = 1;
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serial_update_irq(s);
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}
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}
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static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val)
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{
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SerialState *s = opaque;
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addr &= 7;
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#ifdef DEBUG_SERIAL
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printf("serial: write addr=0x%02x val=0x%02x\n", addr, val);
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#endif
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switch(addr) {
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default:
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case 0:
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if (s->lcr & UART_LCR_DLAB) {
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s->divider = (s->divider & 0xff00) | val;
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serial_update_parameters(s);
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} else {
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s->thr = (uint8_t) val;
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if(s->fcr & UART_FCR_FE) {
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fifo_put(s, XMIT_FIFO, s->thr);
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s->thr_ipending = 0;
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s->lsr &= ~UART_LSR_TEMT;
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s->lsr &= ~UART_LSR_THRE;
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serial_update_irq(s);
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} else {
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s->thr_ipending = 0;
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s->lsr &= ~UART_LSR_THRE;
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serial_update_irq(s);
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}
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serial_xmit(s);
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}
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break;
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case 1:
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if (s->lcr & UART_LCR_DLAB) {
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s->divider = (s->divider & 0x00ff) | (val << 8);
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serial_update_parameters(s);
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} else {
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s->ier = val & 0x0f;
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/* If the backend device is a real serial port, turn polling of the modem
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status lines on physical port on or off depending on UART_IER_MSI state */
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if (s->poll_msl >= 0) {
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if (s->ier & UART_IER_MSI) {
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s->poll_msl = 1;
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serial_update_msl(s);
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} else {
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qemu_del_timer(s->modem_status_poll);
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s->poll_msl = 0;
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}
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}
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if (s->lsr & UART_LSR_THRE) {
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s->thr_ipending = 1;
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serial_update_irq(s);
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}
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}
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break;
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case 2:
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val = val & 0xFF;
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if (s->fcr == val)
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break;
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/* Did the enable/disable flag change? If so, make sure FIFOs get flushed */
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if ((val ^ s->fcr) & UART_FCR_FE)
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val |= UART_FCR_XFR | UART_FCR_RFR;
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/* FIFO clear */
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if (val & UART_FCR_RFR) {
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qemu_del_timer(s->fifo_timeout_timer);
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s->timeout_ipending=0;
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fifo_clear(s,RECV_FIFO);
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}
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if (val & UART_FCR_XFR) {
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fifo_clear(s,XMIT_FIFO);
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}
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if (val & UART_FCR_FE) {
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s->iir |= UART_IIR_FE;
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/* Set RECV_FIFO trigger Level */
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switch (val & 0xC0) {
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case UART_FCR_ITL_1:
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s->recv_fifo.itl = 1;
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break;
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case UART_FCR_ITL_2:
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s->recv_fifo.itl = 4;
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break;
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case UART_FCR_ITL_3:
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s->recv_fifo.itl = 8;
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break;
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case UART_FCR_ITL_4:
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s->recv_fifo.itl = 14;
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break;
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}
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} else
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s->iir &= ~UART_IIR_FE;
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/* Set fcr - or at least the bits in it that are supposed to "stick" */
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s->fcr = val & 0xC9;
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serial_update_irq(s);
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break;
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case 3:
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{
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int break_enable;
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s->lcr = val;
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serial_update_parameters(s);
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break_enable = (val >> 6) & 1;
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if (break_enable != s->last_break_enable) {
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s->last_break_enable = break_enable;
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qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
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&break_enable);
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}
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}
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break;
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case 4:
|
|
{
|
|
int flags;
|
|
int old_mcr = s->mcr;
|
|
s->mcr = val & 0x1f;
|
|
if (val & UART_MCR_LOOP)
|
|
break;
|
|
|
|
if (s->poll_msl >= 0 && old_mcr != s->mcr) {
|
|
|
|
qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags);
|
|
|
|
flags &= ~(CHR_TIOCM_RTS | CHR_TIOCM_DTR);
|
|
|
|
if (val & UART_MCR_RTS)
|
|
flags |= CHR_TIOCM_RTS;
|
|
if (val & UART_MCR_DTR)
|
|
flags |= CHR_TIOCM_DTR;
|
|
|
|
qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_SET_TIOCM, &flags);
|
|
/* Update the modem status after a one-character-send wait-time, since there may be a response
|
|
from the device/computer at the other end of the serial line */
|
|
qemu_mod_timer(s->modem_status_poll, qemu_get_clock(vm_clock) + s->char_transmit_time);
|
|
}
|
|
}
|
|
break;
|
|
case 5:
|
|
break;
|
|
case 6:
|
|
break;
|
|
case 7:
|
|
s->scr = val;
|
|
break;
|
|
}
|
|
}
|
|
|
|
static uint32_t serial_ioport_read(void *opaque, uint32_t addr)
|
|
{
|
|
SerialState *s = opaque;
|
|
uint32_t ret;
|
|
|
|
addr &= 7;
|
|
switch(addr) {
|
|
default:
|
|
case 0:
|
|
if (s->lcr & UART_LCR_DLAB) {
|
|
ret = s->divider & 0xff;
|
|
} else {
|
|
if(s->fcr & UART_FCR_FE) {
|
|
ret = fifo_get(s,RECV_FIFO);
|
|
if (s->recv_fifo.count == 0)
|
|
s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
|
|
else
|
|
qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock (vm_clock) + s->char_transmit_time * 4);
|
|
s->timeout_ipending = 0;
|
|
} else {
|
|
ret = s->rbr;
|
|
s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
|
|
}
|
|
serial_update_irq(s);
|
|
if (!(s->mcr & UART_MCR_LOOP)) {
|
|
/* in loopback mode, don't receive any data */
|
|
qemu_chr_accept_input(s->chr);
|
|
}
|
|
}
|
|
break;
|
|
case 1:
|
|
if (s->lcr & UART_LCR_DLAB) {
|
|
ret = (s->divider >> 8) & 0xff;
|
|
} else {
|
|
ret = s->ier;
|
|
}
|
|
break;
|
|
case 2:
|
|
ret = s->iir;
|
|
s->thr_ipending = 0;
|
|
serial_update_irq(s);
|
|
break;
|
|
case 3:
|
|
ret = s->lcr;
|
|
break;
|
|
case 4:
|
|
ret = s->mcr;
|
|
break;
|
|
case 5:
|
|
ret = s->lsr;
|
|
/* Clear break interrupt */
|
|
if (s->lsr & UART_LSR_BI) {
|
|
s->lsr &= ~UART_LSR_BI;
|
|
serial_update_irq(s);
|
|
}
|
|
break;
|
|
case 6:
|
|
if (s->mcr & UART_MCR_LOOP) {
|
|
/* in loopback, the modem output pins are connected to the
|
|
inputs */
|
|
ret = (s->mcr & 0x0c) << 4;
|
|
ret |= (s->mcr & 0x02) << 3;
|
|
ret |= (s->mcr & 0x01) << 5;
|
|
} else {
|
|
if (s->poll_msl >= 0)
|
|
serial_update_msl(s);
|
|
ret = s->msr;
|
|
/* Clear delta bits & msr int after read, if they were set */
|
|
if (s->msr & UART_MSR_ANY_DELTA) {
|
|
s->msr &= 0xF0;
|
|
serial_update_irq(s);
|
|
}
|
|
}
|
|
break;
|
|
case 7:
|
|
ret = s->scr;
|
|
break;
|
|
}
|
|
#ifdef DEBUG_SERIAL
|
|
printf("serial: read addr=0x%02x val=0x%02x\n", addr, ret);
|
|
#endif
|
|
return ret;
|
|
}
|
|
|
|
static int serial_can_receive(SerialState *s)
|
|
{
|
|
if(s->fcr & UART_FCR_FE) {
|
|
if(s->recv_fifo.count < UART_FIFO_LENGTH)
|
|
/* Advertise (fifo.itl - fifo.count) bytes when count < ITL, and 1 if above. If UART_FIFO_LENGTH - fifo.count is
|
|
advertised the effect will be to almost always fill the fifo completely before the guest has a chance to respond,
|
|
effectively overriding the ITL that the guest has set. */
|
|
return (s->recv_fifo.count <= s->recv_fifo.itl) ? s->recv_fifo.itl - s->recv_fifo.count : 1;
|
|
else
|
|
return 0;
|
|
} else {
|
|
return !(s->lsr & UART_LSR_DR);
|
|
}
|
|
}
|
|
|
|
static void serial_receive_break(SerialState *s)
|
|
{
|
|
s->rbr = 0;
|
|
/* When the LSR_DR is set a null byte is pushed into the fifo */
|
|
fifo_put(s, RECV_FIFO, '\0');
|
|
s->lsr |= UART_LSR_BI | UART_LSR_DR;
|
|
serial_update_irq(s);
|
|
}
|
|
|
|
/* There's data in recv_fifo and s->rbr has not been read for 4 char transmit times */
|
|
static void fifo_timeout_int (void *opaque) {
|
|
SerialState *s = opaque;
|
|
if (s->recv_fifo.count) {
|
|
s->timeout_ipending = 1;
|
|
serial_update_irq(s);
|
|
}
|
|
}
|
|
|
|
static int serial_can_receive1(void *opaque)
|
|
{
|
|
SerialState *s = opaque;
|
|
return serial_can_receive(s);
|
|
}
|
|
|
|
static void serial_receive1(void *opaque, const uint8_t *buf, int size)
|
|
{
|
|
SerialState *s = opaque;
|
|
if(s->fcr & UART_FCR_FE) {
|
|
int i;
|
|
for (i = 0; i < size; i++) {
|
|
fifo_put(s, RECV_FIFO, buf[i]);
|
|
}
|
|
s->lsr |= UART_LSR_DR;
|
|
/* call the timeout receive callback in 4 char transmit time */
|
|
qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock (vm_clock) + s->char_transmit_time * 4);
|
|
} else {
|
|
s->rbr = buf[0];
|
|
s->lsr |= UART_LSR_DR;
|
|
}
|
|
serial_update_irq(s);
|
|
}
|
|
|
|
static void serial_event(void *opaque, int event)
|
|
{
|
|
SerialState *s = opaque;
|
|
#ifdef DEBUG_SERIAL
|
|
printf("serial: event %x\n", event);
|
|
#endif
|
|
if (event == CHR_EVENT_BREAK)
|
|
serial_receive_break(s);
|
|
}
|
|
|
|
static void serial_pre_save(void *opaque)
|
|
{
|
|
SerialState *s = opaque;
|
|
s->fcr_vmstate = s->fcr;
|
|
}
|
|
|
|
static int serial_pre_load(void *opaque)
|
|
{
|
|
SerialState *s = opaque;
|
|
s->fcr_vmstate = 0;
|
|
return 0;
|
|
}
|
|
|
|
static int serial_post_load(void *opaque, int version_id)
|
|
{
|
|
SerialState *s = opaque;
|
|
|
|
/* Initialize fcr via setter to perform essential side-effects */
|
|
serial_ioport_write(s, 0x02, s->fcr_vmstate);
|
|
return 0;
|
|
}
|
|
|
|
static const VMStateDescription vmstate_serial = {
|
|
.name = "serial",
|
|
.version_id = 3,
|
|
.minimum_version_id = 2,
|
|
.pre_save = serial_pre_save,
|
|
.pre_load = serial_pre_load,
|
|
.post_load = serial_post_load,
|
|
.fields = (VMStateField []) {
|
|
VMSTATE_UINT16_V(divider, SerialState, 2),
|
|
VMSTATE_UINT8(rbr, SerialState),
|
|
VMSTATE_UINT8(ier, SerialState),
|
|
VMSTATE_UINT8(iir, SerialState),
|
|
VMSTATE_UINT8(lcr, SerialState),
|
|
VMSTATE_UINT8(mcr, SerialState),
|
|
VMSTATE_UINT8(lsr, SerialState),
|
|
VMSTATE_UINT8(msr, SerialState),
|
|
VMSTATE_UINT8(scr, SerialState),
|
|
VMSTATE_UINT8_V(fcr_vmstate, SerialState, 3),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static void serial_reset(void *opaque)
|
|
{
|
|
SerialState *s = opaque;
|
|
|
|
s->rbr = 0;
|
|
s->ier = 0;
|
|
s->iir = UART_IIR_NO_INT;
|
|
s->lcr = 0;
|
|
s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
|
|
s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS;
|
|
/* Default to 9600 baud, no parity, one stop bit */
|
|
s->divider = 0x0C;
|
|
s->mcr = UART_MCR_OUT2;
|
|
s->scr = 0;
|
|
s->tsr_retry = 0;
|
|
s->char_transmit_time = (get_ticks_per_sec() / 9600) * 9;
|
|
s->poll_msl = 0;
|
|
|
|
fifo_clear(s,RECV_FIFO);
|
|
fifo_clear(s,XMIT_FIFO);
|
|
|
|
s->last_xmit_ts = qemu_get_clock(vm_clock);
|
|
|
|
s->thr_ipending = 0;
|
|
s->last_break_enable = 0;
|
|
qemu_irq_lower(s->irq);
|
|
}
|
|
|
|
static void serial_init_core(SerialState *s)
|
|
{
|
|
if (!s->chr) {
|
|
fprintf(stderr, "Can't create serial device, empty char device\n");
|
|
exit(1);
|
|
}
|
|
|
|
s->modem_status_poll = qemu_new_timer(vm_clock, (QEMUTimerCB *) serial_update_msl, s);
|
|
|
|
s->fifo_timeout_timer = qemu_new_timer(vm_clock, (QEMUTimerCB *) fifo_timeout_int, s);
|
|
s->transmit_timer = qemu_new_timer(vm_clock, (QEMUTimerCB *) serial_xmit, s);
|
|
|
|
qemu_register_reset(serial_reset, s);
|
|
serial_reset(s);
|
|
|
|
qemu_chr_add_handlers(s->chr, serial_can_receive1, serial_receive1,
|
|
serial_event, s);
|
|
}
|
|
|
|
static int serial_isa_initfn(ISADevice *dev)
|
|
{
|
|
ISASerialState *isa = DO_UPCAST(ISASerialState, dev, dev);
|
|
SerialState *s = &isa->state;
|
|
|
|
s->baudbase = 115200;
|
|
isa_init_irq(dev, &s->irq, isa->isairq);
|
|
serial_init_core(s);
|
|
vmstate_register(isa->iobase, &vmstate_serial, s);
|
|
|
|
register_ioport_write(isa->iobase, 8, 1, serial_ioport_write, s);
|
|
register_ioport_read(isa->iobase, 8, 1, serial_ioport_read, s);
|
|
return 0;
|
|
}
|
|
|
|
static const int isa_serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
|
|
static const int isa_serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
|
|
|
|
SerialState *serial_isa_init(int index, CharDriverState *chr)
|
|
{
|
|
ISADevice *dev;
|
|
|
|
dev = isa_create("isa-serial");
|
|
qdev_prop_set_uint32(&dev->qdev, "iobase", isa_serial_io[index]);
|
|
qdev_prop_set_uint32(&dev->qdev, "irq", isa_serial_irq[index]);
|
|
qdev_prop_set_chr(&dev->qdev, "chardev", chr);
|
|
if (qdev_init(&dev->qdev) < 0)
|
|
return NULL;
|
|
return &DO_UPCAST(ISASerialState, dev, dev)->state;
|
|
}
|
|
|
|
SerialState *serial_init(int base, qemu_irq irq, int baudbase,
|
|
CharDriverState *chr)
|
|
{
|
|
SerialState *s;
|
|
|
|
s = qemu_mallocz(sizeof(SerialState));
|
|
|
|
s->irq = irq;
|
|
s->baudbase = baudbase;
|
|
s->chr = chr;
|
|
serial_init_core(s);
|
|
|
|
vmstate_register(base, &vmstate_serial, s);
|
|
|
|
register_ioport_write(base, 8, 1, serial_ioport_write, s);
|
|
register_ioport_read(base, 8, 1, serial_ioport_read, s);
|
|
return s;
|
|
}
|
|
|
|
/* Memory mapped interface */
|
|
static uint32_t serial_mm_readb(void *opaque, target_phys_addr_t addr)
|
|
{
|
|
SerialState *s = opaque;
|
|
|
|
return serial_ioport_read(s, addr >> s->it_shift) & 0xFF;
|
|
}
|
|
|
|
static void serial_mm_writeb(void *opaque, target_phys_addr_t addr,
|
|
uint32_t value)
|
|
{
|
|
SerialState *s = opaque;
|
|
|
|
serial_ioport_write(s, addr >> s->it_shift, value & 0xFF);
|
|
}
|
|
|
|
static uint32_t serial_mm_readw(void *opaque, target_phys_addr_t addr)
|
|
{
|
|
SerialState *s = opaque;
|
|
uint32_t val;
|
|
|
|
val = serial_ioport_read(s, addr >> s->it_shift) & 0xFFFF;
|
|
#ifdef TARGET_WORDS_BIGENDIAN
|
|
val = bswap16(val);
|
|
#endif
|
|
return val;
|
|
}
|
|
|
|
static void serial_mm_writew(void *opaque, target_phys_addr_t addr,
|
|
uint32_t value)
|
|
{
|
|
SerialState *s = opaque;
|
|
#ifdef TARGET_WORDS_BIGENDIAN
|
|
value = bswap16(value);
|
|
#endif
|
|
serial_ioport_write(s, addr >> s->it_shift, value & 0xFFFF);
|
|
}
|
|
|
|
static uint32_t serial_mm_readl(void *opaque, target_phys_addr_t addr)
|
|
{
|
|
SerialState *s = opaque;
|
|
uint32_t val;
|
|
|
|
val = serial_ioport_read(s, addr >> s->it_shift);
|
|
#ifdef TARGET_WORDS_BIGENDIAN
|
|
val = bswap32(val);
|
|
#endif
|
|
return val;
|
|
}
|
|
|
|
static void serial_mm_writel(void *opaque, target_phys_addr_t addr,
|
|
uint32_t value)
|
|
{
|
|
SerialState *s = opaque;
|
|
#ifdef TARGET_WORDS_BIGENDIAN
|
|
value = bswap32(value);
|
|
#endif
|
|
serial_ioport_write(s, addr >> s->it_shift, value);
|
|
}
|
|
|
|
static CPUReadMemoryFunc * const serial_mm_read[] = {
|
|
&serial_mm_readb,
|
|
&serial_mm_readw,
|
|
&serial_mm_readl,
|
|
};
|
|
|
|
static CPUWriteMemoryFunc * const serial_mm_write[] = {
|
|
&serial_mm_writeb,
|
|
&serial_mm_writew,
|
|
&serial_mm_writel,
|
|
};
|
|
|
|
SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
|
|
qemu_irq irq, int baudbase,
|
|
CharDriverState *chr, int ioregister)
|
|
{
|
|
SerialState *s;
|
|
int s_io_memory;
|
|
|
|
s = qemu_mallocz(sizeof(SerialState));
|
|
|
|
s->it_shift = it_shift;
|
|
s->irq = irq;
|
|
s->baudbase = baudbase;
|
|
s->chr = chr;
|
|
|
|
serial_init_core(s);
|
|
vmstate_register(base, &vmstate_serial, s);
|
|
|
|
if (ioregister) {
|
|
s_io_memory = cpu_register_io_memory(serial_mm_read,
|
|
serial_mm_write, s);
|
|
cpu_register_physical_memory(base, 8 << it_shift, s_io_memory);
|
|
}
|
|
serial_update_msl(s);
|
|
return s;
|
|
}
|
|
|
|
static ISADeviceInfo serial_isa_info = {
|
|
.qdev.name = "isa-serial",
|
|
.qdev.size = sizeof(ISASerialState),
|
|
.init = serial_isa_initfn,
|
|
.qdev.props = (Property[]) {
|
|
DEFINE_PROP_HEX32("iobase", ISASerialState, iobase, 0x3f8),
|
|
DEFINE_PROP_UINT32("irq", ISASerialState, isairq, 4),
|
|
DEFINE_PROP_CHR("chardev", ISASerialState, state.chr),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
},
|
|
};
|
|
|
|
static void serial_register_devices(void)
|
|
{
|
|
isa_qdev_register(&serial_isa_info);
|
|
}
|
|
|
|
device_init(serial_register_devices)
|