mirror of https://github.com/proxmox/mirror_qemu
352 lines
9.3 KiB
C
352 lines
9.3 KiB
C
/*
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* i.MX processors GPIO emulation.
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*
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* Copyright (C) 2015 Jean-Christophe Dubois <jcd@tribudubois.net>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 or
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* (at your option) version 3 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "hw/gpio/imx_gpio.h"
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#include "qemu/log.h"
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#ifndef DEBUG_IMX_GPIO
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#define DEBUG_IMX_GPIO 0
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#endif
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typedef enum IMXGPIOLevel {
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IMX_GPIO_LEVEL_LOW = 0,
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IMX_GPIO_LEVEL_HIGH = 1,
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} IMXGPIOLevel;
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#define DPRINTF(fmt, args...) \
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do { \
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if (DEBUG_IMX_GPIO) { \
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fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_GPIO, \
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__func__, ##args); \
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} \
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} while (0)
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static const char *imx_gpio_reg_name(uint32_t reg)
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{
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switch (reg) {
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case DR_ADDR:
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return "DR";
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case GDIR_ADDR:
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return "GDIR";
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case PSR_ADDR:
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return "PSR";
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case ICR1_ADDR:
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return "ICR1";
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case ICR2_ADDR:
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return "ICR2";
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case IMR_ADDR:
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return "IMR";
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case ISR_ADDR:
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return "ISR";
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case EDGE_SEL_ADDR:
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return "EDGE_SEL";
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default:
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return "[?]";
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}
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}
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static void imx_gpio_update_int(IMXGPIOState *s)
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{
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if (s->has_upper_pin_irq) {
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qemu_set_irq(s->irq[0], (s->isr & s->imr & 0x0000FFFF) ? 1 : 0);
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qemu_set_irq(s->irq[1], (s->isr & s->imr & 0xFFFF0000) ? 1 : 0);
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} else {
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qemu_set_irq(s->irq[0], (s->isr & s->imr) ? 1 : 0);
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}
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}
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static void imx_gpio_set_int_line(IMXGPIOState *s, int line, IMXGPIOLevel level)
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{
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/* if this signal isn't configured as an input signal, nothing to do */
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if (!extract32(s->gdir, line, 1)) {
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return;
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}
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/* When set, EDGE_SEL overrides the ICR config */
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if (extract32(s->edge_sel, line, 1)) {
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/* we detect interrupt on rising and falling edge */
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if (extract32(s->psr, line, 1) != level) {
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/* level changed */
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s->isr = deposit32(s->isr, line, 1, 1);
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}
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} else if (extract64(s->icr, 2*line + 1, 1)) {
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/* interrupt is edge sensitive */
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if (extract32(s->psr, line, 1) != level) {
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/* level changed */
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if (extract64(s->icr, 2*line, 1) != level) {
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s->isr = deposit32(s->isr, line, 1, 1);
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}
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}
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} else {
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/* interrupt is level sensitive */
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if (extract64(s->icr, 2*line, 1) == level) {
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s->isr = deposit32(s->isr, line, 1, 1);
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}
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}
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}
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static void imx_gpio_set(void *opaque, int line, int level)
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{
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IMXGPIOState *s = IMX_GPIO(opaque);
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IMXGPIOLevel imx_level = level ? IMX_GPIO_LEVEL_HIGH : IMX_GPIO_LEVEL_LOW;
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imx_gpio_set_int_line(s, line, imx_level);
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/* this is an input signal, so set PSR */
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s->psr = deposit32(s->psr, line, 1, imx_level);
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imx_gpio_update_int(s);
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}
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static void imx_gpio_set_all_int_lines(IMXGPIOState *s)
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{
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int i;
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for (i = 0; i < IMX_GPIO_PIN_COUNT; i++) {
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IMXGPIOLevel imx_level = extract32(s->psr, i, 1);
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imx_gpio_set_int_line(s, i, imx_level);
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}
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imx_gpio_update_int(s);
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}
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static inline void imx_gpio_set_all_output_lines(IMXGPIOState *s)
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{
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int i;
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for (i = 0; i < IMX_GPIO_PIN_COUNT; i++) {
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/*
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* if the line is set as output, then forward the line
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* level to its user.
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*/
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if (extract32(s->gdir, i, 1) && s->output[i]) {
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qemu_set_irq(s->output[i], extract32(s->dr, i, 1));
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}
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}
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}
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static uint64_t imx_gpio_read(void *opaque, hwaddr offset, unsigned size)
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{
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IMXGPIOState *s = IMX_GPIO(opaque);
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uint32_t reg_value = 0;
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switch (offset) {
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case DR_ADDR:
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/*
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* depending on the "line" configuration, the bit values
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* are coming either from DR or PSR
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*/
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reg_value = (s->dr & s->gdir) | (s->psr & ~s->gdir);
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break;
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case GDIR_ADDR:
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reg_value = s->gdir;
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break;
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case PSR_ADDR:
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reg_value = s->psr & ~s->gdir;
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break;
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case ICR1_ADDR:
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reg_value = extract64(s->icr, 0, 32);
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break;
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case ICR2_ADDR:
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reg_value = extract64(s->icr, 32, 32);
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break;
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case IMR_ADDR:
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reg_value = s->imr;
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break;
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case ISR_ADDR:
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reg_value = s->isr;
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break;
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case EDGE_SEL_ADDR:
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if (s->has_edge_sel) {
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reg_value = s->edge_sel;
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} else {
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qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: EDGE_SEL register not "
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"present on this version of GPIO device\n",
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TYPE_IMX_GPIO, __func__);
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}
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
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HWADDR_PRIx "\n", TYPE_IMX_GPIO, __func__, offset);
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break;
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}
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DPRINTF("(%s) = 0x%" PRIx32 "\n", imx_gpio_reg_name(offset), reg_value);
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return reg_value;
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}
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static void imx_gpio_write(void *opaque, hwaddr offset, uint64_t value,
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unsigned size)
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{
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IMXGPIOState *s = IMX_GPIO(opaque);
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DPRINTF("(%s, value = 0x%" PRIx32 ")\n", imx_gpio_reg_name(offset),
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(uint32_t)value);
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switch (offset) {
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case DR_ADDR:
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s->dr = value;
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imx_gpio_set_all_output_lines(s);
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break;
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case GDIR_ADDR:
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s->gdir = value;
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imx_gpio_set_all_output_lines(s);
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imx_gpio_set_all_int_lines(s);
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break;
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case ICR1_ADDR:
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s->icr = deposit64(s->icr, 0, 32, value);
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imx_gpio_set_all_int_lines(s);
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break;
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case ICR2_ADDR:
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s->icr = deposit64(s->icr, 32, 32, value);
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imx_gpio_set_all_int_lines(s);
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break;
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case IMR_ADDR:
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s->imr = value;
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imx_gpio_update_int(s);
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break;
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case ISR_ADDR:
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s->isr |= ~value;
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imx_gpio_set_all_int_lines(s);
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break;
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case EDGE_SEL_ADDR:
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if (s->has_edge_sel) {
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s->edge_sel = value;
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imx_gpio_set_all_int_lines(s);
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} else {
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qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: EDGE_SEL register not "
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"present on this version of GPIO device\n",
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TYPE_IMX_GPIO, __func__);
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}
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
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HWADDR_PRIx "\n", TYPE_IMX_GPIO, __func__, offset);
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break;
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}
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return;
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}
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static const MemoryRegionOps imx_gpio_ops = {
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.read = imx_gpio_read,
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.write = imx_gpio_write,
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.valid.min_access_size = 4,
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.valid.max_access_size = 4,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static const VMStateDescription vmstate_imx_gpio = {
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.name = TYPE_IMX_GPIO,
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(dr, IMXGPIOState),
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VMSTATE_UINT32(gdir, IMXGPIOState),
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VMSTATE_UINT32(psr, IMXGPIOState),
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VMSTATE_UINT64(icr, IMXGPIOState),
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VMSTATE_UINT32(imr, IMXGPIOState),
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VMSTATE_UINT32(isr, IMXGPIOState),
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VMSTATE_BOOL(has_edge_sel, IMXGPIOState),
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VMSTATE_UINT32(edge_sel, IMXGPIOState),
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VMSTATE_END_OF_LIST()
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}
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};
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static Property imx_gpio_properties[] = {
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DEFINE_PROP_BOOL("has-edge-sel", IMXGPIOState, has_edge_sel, true),
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DEFINE_PROP_BOOL("has-upper-pin-irq", IMXGPIOState, has_upper_pin_irq,
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false),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void imx_gpio_reset(DeviceState *dev)
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{
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IMXGPIOState *s = IMX_GPIO(dev);
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s->dr = 0;
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s->gdir = 0;
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s->psr = 0;
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s->icr = 0;
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s->imr = 0;
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s->isr = 0;
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s->edge_sel = 0;
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imx_gpio_set_all_output_lines(s);
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imx_gpio_update_int(s);
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}
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static void imx_gpio_realize(DeviceState *dev, Error **errp)
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{
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IMXGPIOState *s = IMX_GPIO(dev);
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memory_region_init_io(&s->iomem, OBJECT(s), &imx_gpio_ops, s,
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TYPE_IMX_GPIO, IMX_GPIO_MEM_SIZE);
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qdev_init_gpio_in(DEVICE(s), imx_gpio_set, IMX_GPIO_PIN_COUNT);
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qdev_init_gpio_out(DEVICE(s), s->output, IMX_GPIO_PIN_COUNT);
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sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[0]);
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sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[1]);
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sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
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}
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static void imx_gpio_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = imx_gpio_realize;
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dc->reset = imx_gpio_reset;
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dc->props = imx_gpio_properties;
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dc->vmsd = &vmstate_imx_gpio;
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dc->desc = "i.MX GPIO controller";
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}
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static const TypeInfo imx_gpio_info = {
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.name = TYPE_IMX_GPIO,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(IMXGPIOState),
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.class_init = imx_gpio_class_init,
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};
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static void imx_gpio_register_types(void)
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{
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type_register_static(&imx_gpio_info);
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}
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type_init(imx_gpio_register_types)
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