mirror of https://github.com/proxmox/mirror_qemu
193 lines
6.1 KiB
C
193 lines
6.1 KiB
C
/*
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* Coherent Processing System emulation.
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*
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* Copyright (c) 2016 Imagination Technologies
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "hw/mips/cps.h"
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#include "hw/mips/mips.h"
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#include "hw/mips/cpudevs.h"
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#include "sysemu/kvm.h"
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qemu_irq get_cps_irq(MIPSCPSState *s, int pin_number)
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{
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assert(pin_number < s->num_irq);
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return s->gic.irq_state[pin_number].irq;
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}
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static void mips_cps_init(Object *obj)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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MIPSCPSState *s = MIPS_CPS(obj);
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/* Cover entire address space as there do not seem to be any
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* constraints for the base address of CPC and GIC. */
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memory_region_init(&s->container, obj, "mips-cps-container", UINT64_MAX);
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sysbus_init_mmio(sbd, &s->container);
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}
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static void main_cpu_reset(void *opaque)
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{
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MIPSCPU *cpu = opaque;
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CPUState *cs = CPU(cpu);
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cpu_reset(cs);
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/* All VPs are halted on reset. Leave powering up to CPC. */
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cs->halted = 1;
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}
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static bool cpu_mips_itu_supported(CPUMIPSState *env)
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{
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bool is_mt = (env->CP0_Config5 & (1 << CP0C5_VP)) ||
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(env->CP0_Config3 & (1 << CP0C3_MT));
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return is_mt && !kvm_enabled();
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}
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static void mips_cps_realize(DeviceState *dev, Error **errp)
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{
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MIPSCPSState *s = MIPS_CPS(dev);
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CPUMIPSState *env;
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MIPSCPU *cpu;
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int i;
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Error *err = NULL;
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target_ulong gcr_base;
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bool itu_present = false;
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for (i = 0; i < s->num_vp; i++) {
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cpu = cpu_mips_init(s->cpu_model);
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if (cpu == NULL) {
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error_setg(errp, "%s: CPU initialization failed\n", __func__);
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return;
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}
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/* Init internal devices */
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cpu_mips_irq_init_cpu(cpu);
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cpu_mips_clock_init(cpu);
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env = &cpu->env;
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if (cpu_mips_itu_supported(env)) {
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itu_present = true;
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/* Attach ITC Tag to the VP */
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env->itc_tag = mips_itu_get_tag_region(&s->itu);
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}
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qemu_register_reset(main_cpu_reset, cpu);
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}
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cpu = MIPS_CPU(first_cpu);
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env = &cpu->env;
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/* Inter-Thread Communication Unit */
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if (itu_present) {
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object_initialize(&s->itu, sizeof(s->itu), TYPE_MIPS_ITU);
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qdev_set_parent_bus(DEVICE(&s->itu), sysbus_get_default());
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object_property_set_int(OBJECT(&s->itu), 16, "num-fifo", &err);
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object_property_set_int(OBJECT(&s->itu), 16, "num-semaphores", &err);
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object_property_set_bool(OBJECT(&s->itu), true, "realized", &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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memory_region_add_subregion(&s->container, 0,
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sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->itu), 0));
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}
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/* Cluster Power Controller */
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object_initialize(&s->cpc, sizeof(s->cpc), TYPE_MIPS_CPC);
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qdev_set_parent_bus(DEVICE(&s->cpc), sysbus_get_default());
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object_property_set_int(OBJECT(&s->cpc), s->num_vp, "num-vp", &err);
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object_property_set_int(OBJECT(&s->cpc), 1, "vp-start-running", &err);
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object_property_set_bool(OBJECT(&s->cpc), true, "realized", &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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memory_region_add_subregion(&s->container, 0,
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sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpc), 0));
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/* Global Interrupt Controller */
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object_initialize(&s->gic, sizeof(s->gic), TYPE_MIPS_GIC);
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qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default());
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object_property_set_int(OBJECT(&s->gic), s->num_vp, "num-vp", &err);
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object_property_set_int(OBJECT(&s->gic), 128, "num-irq", &err);
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object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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memory_region_add_subregion(&s->container, 0,
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sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gic), 0));
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/* Global Configuration Registers */
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gcr_base = env->CP0_CMGCRBase << 4;
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object_initialize(&s->gcr, sizeof(s->gcr), TYPE_MIPS_GCR);
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qdev_set_parent_bus(DEVICE(&s->gcr), sysbus_get_default());
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object_property_set_int(OBJECT(&s->gcr), s->num_vp, "num-vp", &err);
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object_property_set_int(OBJECT(&s->gcr), 0x800, "gcr-rev", &err);
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object_property_set_int(OBJECT(&s->gcr), gcr_base, "gcr-base", &err);
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object_property_set_link(OBJECT(&s->gcr), OBJECT(&s->gic.mr), "gic", &err);
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object_property_set_link(OBJECT(&s->gcr), OBJECT(&s->cpc.mr), "cpc", &err);
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object_property_set_bool(OBJECT(&s->gcr), true, "realized", &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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memory_region_add_subregion(&s->container, gcr_base,
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sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gcr), 0));
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}
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static Property mips_cps_properties[] = {
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DEFINE_PROP_UINT32("num-vp", MIPSCPSState, num_vp, 1),
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DEFINE_PROP_UINT32("num-irq", MIPSCPSState, num_irq, 256),
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DEFINE_PROP_STRING("cpu-model", MIPSCPSState, cpu_model),
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DEFINE_PROP_END_OF_LIST()
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};
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static void mips_cps_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = mips_cps_realize;
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dc->props = mips_cps_properties;
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}
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static const TypeInfo mips_cps_info = {
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.name = TYPE_MIPS_CPS,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(MIPSCPSState),
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.instance_init = mips_cps_init,
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.class_init = mips_cps_class_init,
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};
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static void mips_cps_register_types(void)
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{
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type_register_static(&mips_cps_info);
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}
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type_init(mips_cps_register_types)
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