mirror of https://github.com/proxmox/mirror_qemu
471 lines
14 KiB
C
471 lines
14 KiB
C
/*
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* ASPEED AST2400 SMC Controller (SPI Flash Only)
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*
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* Copyright (C) 2016 IBM Corp.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "hw/sysbus.h"
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#include "sysemu/sysemu.h"
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#include "qemu/log.h"
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#include "include/qemu/error-report.h"
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#include "exec/address-spaces.h"
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#include "hw/ssi/aspeed_smc.h"
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/* CE Type Setting Register */
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#define R_CONF (0x00 / 4)
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#define CONF_LEGACY_DISABLE (1 << 31)
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#define CONF_ENABLE_W4 20
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#define CONF_ENABLE_W3 19
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#define CONF_ENABLE_W2 18
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#define CONF_ENABLE_W1 17
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#define CONF_ENABLE_W0 16
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#define CONF_FLASH_TYPE4 9
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#define CONF_FLASH_TYPE3 7
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#define CONF_FLASH_TYPE2 5
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#define CONF_FLASH_TYPE1 3
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#define CONF_FLASH_TYPE0 1
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/* CE Control Register */
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#define R_CE_CTRL (0x04 / 4)
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#define CTRL_EXTENDED4 4 /* 32 bit addressing for SPI */
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#define CTRL_EXTENDED3 3 /* 32 bit addressing for SPI */
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#define CTRL_EXTENDED2 2 /* 32 bit addressing for SPI */
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#define CTRL_EXTENDED1 1 /* 32 bit addressing for SPI */
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#define CTRL_EXTENDED0 0 /* 32 bit addressing for SPI */
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/* Interrupt Control and Status Register */
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#define R_INTR_CTRL (0x08 / 4)
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#define INTR_CTRL_DMA_STATUS (1 << 11)
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#define INTR_CTRL_CMD_ABORT_STATUS (1 << 10)
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#define INTR_CTRL_WRITE_PROTECT_STATUS (1 << 9)
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#define INTR_CTRL_DMA_EN (1 << 3)
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#define INTR_CTRL_CMD_ABORT_EN (1 << 2)
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#define INTR_CTRL_WRITE_PROTECT_EN (1 << 1)
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/* CEx Control Register */
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#define R_CTRL0 (0x10 / 4)
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#define CTRL_CMD_SHIFT 16
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#define CTRL_CMD_MASK 0xff
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#define CTRL_CE_STOP_ACTIVE (1 << 2)
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#define CTRL_CMD_MODE_MASK 0x3
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#define CTRL_READMODE 0x0
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#define CTRL_FREADMODE 0x1
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#define CTRL_WRITEMODE 0x2
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#define CTRL_USERMODE 0x3
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#define R_CTRL1 (0x14 / 4)
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#define R_CTRL2 (0x18 / 4)
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#define R_CTRL3 (0x1C / 4)
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#define R_CTRL4 (0x20 / 4)
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/* CEx Segment Address Register */
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#define R_SEG_ADDR0 (0x30 / 4)
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#define SEG_SIZE_SHIFT 24 /* 8MB units */
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#define SEG_SIZE_MASK 0x7f
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#define SEG_START_SHIFT 16 /* address bit [A29-A23] */
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#define SEG_START_MASK 0x7f
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#define R_SEG_ADDR1 (0x34 / 4)
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#define R_SEG_ADDR2 (0x38 / 4)
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#define R_SEG_ADDR3 (0x3C / 4)
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#define R_SEG_ADDR4 (0x40 / 4)
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/* Misc Control Register #1 */
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#define R_MISC_CTRL1 (0x50 / 4)
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/* Misc Control Register #2 */
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#define R_MISC_CTRL2 (0x54 / 4)
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/* DMA Control/Status Register */
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#define R_DMA_CTRL (0x80 / 4)
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#define DMA_CTRL_DELAY_MASK 0xf
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#define DMA_CTRL_DELAY_SHIFT 8
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#define DMA_CTRL_FREQ_MASK 0xf
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#define DMA_CTRL_FREQ_SHIFT 4
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#define DMA_CTRL_MODE (1 << 3)
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#define DMA_CTRL_CKSUM (1 << 2)
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#define DMA_CTRL_DIR (1 << 1)
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#define DMA_CTRL_EN (1 << 0)
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/* DMA Flash Side Address */
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#define R_DMA_FLASH_ADDR (0x84 / 4)
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/* DMA DRAM Side Address */
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#define R_DMA_DRAM_ADDR (0x88 / 4)
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/* DMA Length Register */
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#define R_DMA_LEN (0x8C / 4)
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/* Checksum Calculation Result */
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#define R_DMA_CHECKSUM (0x90 / 4)
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/* Misc Control Register #2 */
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#define R_TIMINGS (0x94 / 4)
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/* SPI controller registers and bits */
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#define R_SPI_CONF (0x00 / 4)
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#define SPI_CONF_ENABLE_W0 0
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#define R_SPI_CTRL0 (0x4 / 4)
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#define R_SPI_MISC_CTRL (0x10 / 4)
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#define R_SPI_TIMINGS (0x14 / 4)
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/*
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* Default segments mapping addresses and size for each slave per
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* controller. These can be changed when board is initialized with the
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* Segment Address Registers but they don't seem do be used on the
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* field.
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*/
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static const AspeedSegments aspeed_segments_legacy[] = {
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{ 0x10000000, 32 * 1024 * 1024 },
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};
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static const AspeedSegments aspeed_segments_fmc[] = {
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{ 0x20000000, 64 * 1024 * 1024 },
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{ 0x24000000, 32 * 1024 * 1024 },
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{ 0x26000000, 32 * 1024 * 1024 },
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{ 0x28000000, 32 * 1024 * 1024 },
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{ 0x2A000000, 32 * 1024 * 1024 }
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};
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static const AspeedSegments aspeed_segments_spi[] = {
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{ 0x30000000, 64 * 1024 * 1024 },
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};
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static const AspeedSMCController controllers[] = {
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{ "aspeed.smc.smc", R_CONF, R_CE_CTRL, R_CTRL0, R_TIMINGS,
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CONF_ENABLE_W0, 5, aspeed_segments_legacy, 0x6000000 },
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{ "aspeed.smc.fmc", R_CONF, R_CE_CTRL, R_CTRL0, R_TIMINGS,
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CONF_ENABLE_W0, 5, aspeed_segments_fmc, 0x10000000 },
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{ "aspeed.smc.spi", R_SPI_CONF, 0xff, R_SPI_CTRL0, R_SPI_TIMINGS,
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SPI_CONF_ENABLE_W0, 1, aspeed_segments_spi, 0x10000000 },
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};
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static uint64_t aspeed_smc_flash_default_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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qemu_log_mask(LOG_GUEST_ERROR, "%s: To 0x%" HWADDR_PRIx " of size %u"
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PRIx64 "\n", __func__, addr, size);
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return 0;
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}
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static void aspeed_smc_flash_default_write(void *opaque, hwaddr addr,
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uint64_t data, unsigned size)
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{
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qemu_log_mask(LOG_GUEST_ERROR, "%s: To 0x%" HWADDR_PRIx " of size %u: 0x%"
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PRIx64 "\n", __func__, addr, size, data);
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}
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static const MemoryRegionOps aspeed_smc_flash_default_ops = {
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.read = aspeed_smc_flash_default_read,
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.write = aspeed_smc_flash_default_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 1,
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.max_access_size = 4,
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},
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};
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static inline int aspeed_smc_flash_mode(const AspeedSMCState *s, int cs)
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{
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return s->regs[s->r_ctrl0 + cs] & CTRL_CMD_MODE_MASK;
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}
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static inline bool aspeed_smc_is_usermode(const AspeedSMCState *s, int cs)
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{
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return aspeed_smc_flash_mode(s, cs) == CTRL_USERMODE;
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}
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static inline bool aspeed_smc_is_writable(const AspeedSMCState *s, int cs)
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{
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return s->regs[s->r_conf] & (1 << (s->conf_enable_w0 + cs));
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}
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static uint64_t aspeed_smc_flash_read(void *opaque, hwaddr addr, unsigned size)
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{
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AspeedSMCFlash *fl = opaque;
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const AspeedSMCState *s = fl->controller;
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uint64_t ret = 0;
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int i;
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if (aspeed_smc_is_usermode(s, fl->id)) {
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for (i = 0; i < size; i++) {
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ret |= ssi_transfer(s->spi, 0x0) << (8 * i);
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}
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} else {
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qemu_log_mask(LOG_UNIMP, "%s: usermode not implemented\n",
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__func__);
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ret = -1;
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}
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return ret;
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}
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static void aspeed_smc_flash_write(void *opaque, hwaddr addr, uint64_t data,
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unsigned size)
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{
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AspeedSMCFlash *fl = opaque;
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const AspeedSMCState *s = fl->controller;
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int i;
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if (!aspeed_smc_is_writable(s, fl->id)) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: flash is not writable at 0x%"
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HWADDR_PRIx "\n", __func__, addr);
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return;
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}
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if (!aspeed_smc_is_usermode(s, fl->id)) {
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qemu_log_mask(LOG_UNIMP, "%s: usermode not implemented\n",
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__func__);
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return;
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}
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for (i = 0; i < size; i++) {
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ssi_transfer(s->spi, (data >> (8 * i)) & 0xff);
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}
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}
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static const MemoryRegionOps aspeed_smc_flash_ops = {
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.read = aspeed_smc_flash_read,
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.write = aspeed_smc_flash_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 1,
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.max_access_size = 4,
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},
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};
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static bool aspeed_smc_is_ce_stop_active(const AspeedSMCState *s, int cs)
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{
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return s->regs[s->r_ctrl0 + cs] & CTRL_CE_STOP_ACTIVE;
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}
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static void aspeed_smc_update_cs(const AspeedSMCState *s)
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{
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int i;
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for (i = 0; i < s->num_cs; ++i) {
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qemu_set_irq(s->cs_lines[i], aspeed_smc_is_ce_stop_active(s, i));
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}
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}
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static void aspeed_smc_reset(DeviceState *d)
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{
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AspeedSMCState *s = ASPEED_SMC(d);
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int i;
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memset(s->regs, 0, sizeof s->regs);
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/* Unselect all slaves */
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for (i = 0; i < s->num_cs; ++i) {
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s->regs[s->r_ctrl0 + i] |= CTRL_CE_STOP_ACTIVE;
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}
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aspeed_smc_update_cs(s);
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}
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static bool aspeed_smc_is_implemented(AspeedSMCState *s, hwaddr addr)
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{
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return (addr == s->r_conf || addr == s->r_timings || addr == s->r_ce_ctrl ||
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(addr >= s->r_ctrl0 && addr < s->r_ctrl0 + s->num_cs));
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}
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static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int size)
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{
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AspeedSMCState *s = ASPEED_SMC(opaque);
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addr >>= 2;
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if (addr >= ARRAY_SIZE(s->regs)) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Out-of-bounds read at 0x%" HWADDR_PRIx "\n",
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__func__, addr);
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return 0;
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}
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if (!aspeed_smc_is_implemented(s, addr)) {
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qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\n",
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__func__, addr);
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return 0;
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}
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return s->regs[addr];
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}
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static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data,
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unsigned int size)
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{
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AspeedSMCState *s = ASPEED_SMC(opaque);
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uint32_t value = data;
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addr >>= 2;
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if (addr >= ARRAY_SIZE(s->regs)) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Out-of-bounds write at 0x%" HWADDR_PRIx "\n",
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__func__, addr);
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return;
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}
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if (!aspeed_smc_is_implemented(s, addr)) {
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qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\n",
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__func__, addr);
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return;
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}
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/*
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* Not much to do apart from storing the value and set the cs
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* lines if the register is a controlling one.
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*/
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s->regs[addr] = value;
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if (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + s->num_cs) {
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aspeed_smc_update_cs(s);
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}
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}
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static const MemoryRegionOps aspeed_smc_ops = {
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.read = aspeed_smc_read,
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.write = aspeed_smc_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid.unaligned = true,
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};
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static void aspeed_smc_realize(DeviceState *dev, Error **errp)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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AspeedSMCState *s = ASPEED_SMC(dev);
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AspeedSMCClass *mc = ASPEED_SMC_GET_CLASS(s);
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int i;
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char name[32];
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hwaddr offset = 0;
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s->ctrl = mc->ctrl;
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/* keep a copy under AspeedSMCState to speed up accesses */
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s->r_conf = s->ctrl->r_conf;
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s->r_ce_ctrl = s->ctrl->r_ce_ctrl;
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s->r_ctrl0 = s->ctrl->r_ctrl0;
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s->r_timings = s->ctrl->r_timings;
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s->conf_enable_w0 = s->ctrl->conf_enable_w0;
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/* Enforce some real HW limits */
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if (s->num_cs > s->ctrl->max_slaves) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: num_cs cannot exceed: %d\n",
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__func__, s->ctrl->max_slaves);
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s->num_cs = s->ctrl->max_slaves;
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}
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s->spi = ssi_create_bus(dev, "spi");
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/* Setup cs_lines for slaves */
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sysbus_init_irq(sbd, &s->irq);
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s->cs_lines = g_new0(qemu_irq, s->num_cs);
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ssi_auto_connect_slaves(dev, s->cs_lines, s->spi);
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for (i = 0; i < s->num_cs; ++i) {
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sysbus_init_irq(sbd, &s->cs_lines[i]);
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}
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aspeed_smc_reset(dev);
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memory_region_init_io(&s->mmio, OBJECT(s), &aspeed_smc_ops, s,
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s->ctrl->name, ASPEED_SMC_R_MAX * 4);
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sysbus_init_mmio(sbd, &s->mmio);
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/*
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* Memory region where flash modules are remapped
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*/
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snprintf(name, sizeof(name), "%s.flash", s->ctrl->name);
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memory_region_init_io(&s->mmio_flash, OBJECT(s),
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&aspeed_smc_flash_default_ops, s, name,
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s->ctrl->mapping_window_size);
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sysbus_init_mmio(sbd, &s->mmio_flash);
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s->flashes = g_new0(AspeedSMCFlash, s->num_cs);
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for (i = 0; i < s->num_cs; ++i) {
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AspeedSMCFlash *fl = &s->flashes[i];
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snprintf(name, sizeof(name), "%s.%d", s->ctrl->name, i);
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fl->id = i;
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fl->controller = s;
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fl->size = s->ctrl->segments[i].size;
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memory_region_init_io(&fl->mmio, OBJECT(s), &aspeed_smc_flash_ops,
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fl, name, fl->size);
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memory_region_add_subregion(&s->mmio_flash, offset, &fl->mmio);
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offset += fl->size;
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}
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}
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static const VMStateDescription vmstate_aspeed_smc = {
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.name = "aspeed.smc",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(regs, AspeedSMCState, ASPEED_SMC_R_MAX),
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VMSTATE_END_OF_LIST()
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}
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};
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static Property aspeed_smc_properties[] = {
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DEFINE_PROP_UINT32("num-cs", AspeedSMCState, num_cs, 1),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void aspeed_smc_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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AspeedSMCClass *mc = ASPEED_SMC_CLASS(klass);
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dc->realize = aspeed_smc_realize;
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dc->reset = aspeed_smc_reset;
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dc->props = aspeed_smc_properties;
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dc->vmsd = &vmstate_aspeed_smc;
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mc->ctrl = data;
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}
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static const TypeInfo aspeed_smc_info = {
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.name = TYPE_ASPEED_SMC,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(AspeedSMCState),
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.class_size = sizeof(AspeedSMCClass),
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.abstract = true,
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};
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static void aspeed_smc_register_types(void)
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{
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int i;
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type_register_static(&aspeed_smc_info);
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for (i = 0; i < ARRAY_SIZE(controllers); ++i) {
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TypeInfo ti = {
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.name = controllers[i].name,
|
|
.parent = TYPE_ASPEED_SMC,
|
|
.class_init = aspeed_smc_class_init,
|
|
.class_data = (void *)&controllers[i],
|
|
};
|
|
type_register(&ti);
|
|
}
|
|
}
|
|
|
|
type_init(aspeed_smc_register_types)
|