mirror of https://github.com/proxmox/mirror_qemu
![]() - Vector extension bug fixes - Bit manipulation extension bug fix - Support vhost-user and numa mem options on all boards - Rationalise XLEN and operand lengths - Bump the OpenTitan FPGA support - Remove the Ibex PLIC - General code cleanup -----BEGIN PGP SIGNATURE----- iQEzBAABCAAdFiEE9sSsRtSTSGjTuM6PIeENKd+XcFQFAmFyvkoACgkQIeENKd+X cFRvOQgAmSgFMu7BbiuLJ7W/0kK/a8vM53+HAMFyFvYiTS7ae2NRmxKyeR/OhFLf qm36G/SbBhymWAvJysACa7mjvn104WnXkMdhLYGimkne/65IbnQOImzpXk81WP/n 45p/y0DdCs5pP2JNf9aIVxMMzgH2Lo4IgKxLFz+qpnphxtZGjdpocrCz837BOZQH p61hadfi3rTc06w0Auq8A4Zr+Rp/gpoGzXmB0ujfRGfqi+brg40TV4EAX33e3BJi 249922MbFy2KqqO8H8So9rTZiK4gb/KJ0vGp61nwPcGsf1JPWXpeeb2g6L1syXHW 8J9VezmnIs8bs2SXDvkf0aZpEvDrIA== =AKR1 -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/alistair23/tags/pull-riscv-to-apply-20211022-2' into staging Fourth RISC-V PR for QEMU 6.2 - Vector extension bug fixes - Bit manipulation extension bug fix - Support vhost-user and numa mem options on all boards - Rationalise XLEN and operand lengths - Bump the OpenTitan FPGA support - Remove the Ibex PLIC - General code cleanup # gpg: Signature made Fri 22 Oct 2021 06:36:10 AM PDT # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full] * remotes/alistair23/tags/pull-riscv-to-apply-20211022-2: (33 commits) hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_id hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram_id hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram_id hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram_id hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_id hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id hw/intc: sifive_plic: Cleanup the irq_request function hw/intc: sifive_plic: Cleanup the realize function hw/intc: sifive_plic: Move the properties hw/intc: Remove the Ibex PLIC hw/riscv: opentitan: Update to the latest build target/riscv: Compute mstatus.sd on demand target/riscv: Use riscv_csrrw_debug for cpu_dump target/riscv: Use gen_shift*_per_ol for RVB, RVI target/riscv: Use gen_unary_per_ol for RVB target/riscv: Adjust trans_rev8_32 for riscv64 target/riscv: Use gen_arith_per_ol for RVM target/riscv: Replace DisasContext.w with DisasContext.ol target/riscv: Replace is_32bit with get_xl/get_xlen target/riscv: Properly check SEW in amo_op ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
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.. | ||
acpi | ||
adc | ||
arm | ||
audio | ||
block | ||
char | ||
core | ||
cpu | ||
cris | ||
display | ||
dma | ||
firmware | ||
gpio | ||
hyperv | ||
i2c | ||
i386 | ||
ide | ||
input | ||
intc | ||
ipack | ||
ipmi | ||
isa | ||
kvm | ||
m68k | ||
mem | ||
mips | ||
misc | ||
net | ||
nubus | ||
nvram | ||
pci | ||
pci-bridge | ||
pci-host | ||
ppc | ||
rdma | ||
remote | ||
riscv | ||
rtc | ||
rx | ||
s390x | ||
scsi | ||
sd | ||
sensor | ||
sh4 | ||
southbridge | ||
sparc | ||
ssi | ||
timer | ||
tricore | ||
usb | ||
vfio | ||
virtio | ||
watchdog | ||
xen | ||
xtensa | ||
boards.h | ||
clock.h | ||
elf_ops.h | ||
fw-path-provider.h | ||
hotplug.h | ||
hw.h | ||
ide.h | ||
irq.h | ||
loader-fit.h | ||
loader.h | ||
nmi.h | ||
or-irq.h | ||
pcmcia.h | ||
platform-bus.h | ||
ptimer.h | ||
qdev-clock.h | ||
qdev-core.h | ||
qdev-dma.h | ||
qdev-properties-system.h | ||
qdev-properties.h | ||
register.h | ||
registerfields.h | ||
resettable.h | ||
stream.h | ||
sysbus.h | ||
usb.h | ||
vmstate-if.h |