mirror_qemu/target/mips
Huacai Chen af868995e1 target/mips: Add Loongson-3 CPU definition
Loongson-3 CPU family include Loongson-3A R1/R2/R3/R4 and Loongson-3B
R1/R2. Loongson-3A R1 is the oldest and its ISA is the smallest, while
Loongson-3A R4 is the newest and its ISA is almost the superset of all
others. To reduce complexity, we just define two CPU types:

1) "Loongson-3A1000" CPU which is corresponding to Loongson-3A R1. It is
   suitable for TCG because Loongson-3A R1 has fewest ASE.
2) "Loongson-3A4000" CPU which is corresponding to Loongson-3A R4. It is
   suitable for KVM because Loongson-3A R4 has the VZ ASE.

Loongson-3A has CONFIG6 and CONFIG7, so add their bit-fields as well.

[AM: Rearranged insn_flags, added comments, renamed lmi_helper.c,
improved commit message, fixed checkpatch warnings]

Signed-off-by: Huacai Chen <chenhc@lemote.com>
Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Message-Id: <1591065557-9174-3-git-send-email-chenhc@lemote.com>
2020-06-09 17:32:45 +02:00
..
Makefile.objs target/mips: Add Loongson-3 CPU definition 2020-06-09 17:32:45 +02:00
TODO
cp0_helper.c target/mips: Separate CP0-related helpers into their own file 2020-02-04 08:53:54 +01:00
cp0_timer.c target/mips: Style improvements in cp0_timer.c 2019-08-19 19:53:37 +02:00
cpu-param.h target/mips: Support variable page size 2020-06-01 13:28:21 +02:00
cpu-qom.h cpu: Use DeviceClass reset instead of a special CPUClass reset 2020-03-17 19:48:10 -04:00
cpu.c cpu: Use DeviceClass reset instead of a special CPUClass reset 2020-03-17 19:48:10 -04:00
cpu.h target/mips: Add Loongson-3 CPU definition 2020-06-09 17:32:45 +02:00
dsp_helper.c target/mips: Clean up dsp_helper.c 2019-06-01 20:20:20 +02:00
fpu_helper.c target/mips: fpu: Refactor conversion from ieee to mips exception flags 2020-06-09 17:32:45 +02:00
gdbstub.c gdbstub: extend GByteArray to read register helpers 2020-03-17 17:38:38 +00:00
helper.c target/mips: Add implementation of GINVT instruction 2020-01-29 19:28:52 +01:00
helper.h target/mips: Add implementation of GINVT instruction 2020-01-29 19:28:52 +01:00
internal.h target/mips: Add Loongson-3 CPU definition 2020-06-09 17:32:45 +02:00
kvm.c target/mips: Add more CP0 register for save/restore 2020-06-01 13:28:21 +02:00
kvm_mips.h target/mips: Clean up kvm_mips.h 2019-10-01 16:37:50 +02:00
lmmi_helper.c target/mips: Add Loongson-3 CPU definition 2020-06-09 17:32:45 +02:00
machine.c target/mips: Add more CP0 register for save/restore 2020-06-01 13:28:21 +02:00
mips-defs.h target/mips: Add Loongson-3 CPU definition 2020-06-09 17:32:45 +02:00
mips-semi.c target/mips: semihosting: Remove 'uhi_done' label in helper_do_semihosting() 2020-01-29 19:28:52 +01:00
msa_helper.c target/mips: fpu: Refactor conversion from ieee to mips exception flags 2020-06-09 17:32:45 +02:00
op_helper.c target/mips: Separate FPU-related helpers into their own file 2020-02-04 08:53:54 +01:00
trace-events trace-events: Shorten file names in comments 2019-03-22 16:18:07 +00:00
translate.c target/mips: Add Loongson-3 CPU definition 2020-06-09 17:32:45 +02:00
translate_init.inc.c target/mips: Add Loongson-3 CPU definition 2020-06-09 17:32:45 +02:00