mirror of https://github.com/proxmox/mirror_qemu
413 lines
11 KiB
C
413 lines
11 KiB
C
/*
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* OMAP LCD controller.
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*
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* Copyright (C) 2006-2007 Andrzej Zaborowski <balrog@zabor.org>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hw/hw.h"
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#include "ui/console.h"
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#include "hw/arm/omap.h"
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#include "framebuffer.h"
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#include "ui/pixel_ops.h"
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struct omap_lcd_panel_s {
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MemoryRegion *sysmem;
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MemoryRegion iomem;
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qemu_irq irq;
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QemuConsole *con;
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int plm;
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int tft;
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int mono;
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int enable;
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int width;
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int height;
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int interrupts;
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uint32_t timing[3];
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uint32_t subpanel;
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uint32_t ctrl;
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struct omap_dma_lcd_channel_s *dma;
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uint16_t palette[256];
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int palette_done;
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int frame_done;
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int invalidate;
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int sync_error;
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};
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static void omap_lcd_interrupts(struct omap_lcd_panel_s *s)
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{
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if (s->frame_done && (s->interrupts & 1)) {
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qemu_irq_raise(s->irq);
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return;
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}
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if (s->palette_done && (s->interrupts & 2)) {
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qemu_irq_raise(s->irq);
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return;
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}
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if (s->sync_error) {
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qemu_irq_raise(s->irq);
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return;
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}
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qemu_irq_lower(s->irq);
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}
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#define draw_line_func drawfn
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#define DEPTH 8
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#include "omap_lcd_template.h"
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#define DEPTH 15
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#include "omap_lcd_template.h"
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#define DEPTH 16
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#include "omap_lcd_template.h"
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#define DEPTH 32
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#include "omap_lcd_template.h"
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static draw_line_func draw_line_table2[33] = {
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[0 ... 32] = NULL,
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[8] = draw_line2_8,
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[15] = draw_line2_15,
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[16] = draw_line2_16,
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[32] = draw_line2_32,
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}, draw_line_table4[33] = {
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[0 ... 32] = NULL,
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[8] = draw_line4_8,
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[15] = draw_line4_15,
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[16] = draw_line4_16,
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[32] = draw_line4_32,
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}, draw_line_table8[33] = {
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[0 ... 32] = NULL,
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[8] = draw_line8_8,
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[15] = draw_line8_15,
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[16] = draw_line8_16,
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[32] = draw_line8_32,
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}, draw_line_table12[33] = {
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[0 ... 32] = NULL,
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[8] = draw_line12_8,
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[15] = draw_line12_15,
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[16] = draw_line12_16,
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[32] = draw_line12_32,
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}, draw_line_table16[33] = {
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[0 ... 32] = NULL,
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[8] = draw_line16_8,
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[15] = draw_line16_15,
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[16] = draw_line16_16,
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[32] = draw_line16_32,
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};
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static void omap_update_display(void *opaque)
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{
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struct omap_lcd_panel_s *omap_lcd = (struct omap_lcd_panel_s *) opaque;
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DisplaySurface *surface = qemu_console_surface(omap_lcd->con);
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draw_line_func draw_line;
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int size, height, first, last;
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int width, linesize, step, bpp, frame_offset;
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hwaddr frame_base;
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if (!omap_lcd || omap_lcd->plm == 1 || !omap_lcd->enable ||
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!surface_bits_per_pixel(surface)) {
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return;
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}
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frame_offset = 0;
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if (omap_lcd->plm != 2) {
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cpu_physical_memory_read(omap_lcd->dma->phys_framebuffer[
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omap_lcd->dma->current_frame],
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(void *)omap_lcd->palette, 0x200);
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switch (omap_lcd->palette[0] >> 12 & 7) {
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case 3 ... 7:
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frame_offset += 0x200;
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break;
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default:
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frame_offset += 0x20;
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}
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}
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/* Colour depth */
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switch ((omap_lcd->palette[0] >> 12) & 7) {
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case 1:
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draw_line = draw_line_table2[surface_bits_per_pixel(surface)];
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bpp = 2;
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break;
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case 2:
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draw_line = draw_line_table4[surface_bits_per_pixel(surface)];
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bpp = 4;
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break;
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case 3:
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draw_line = draw_line_table8[surface_bits_per_pixel(surface)];
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bpp = 8;
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break;
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case 4 ... 7:
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if (!omap_lcd->tft)
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draw_line = draw_line_table12[surface_bits_per_pixel(surface)];
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else
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draw_line = draw_line_table16[surface_bits_per_pixel(surface)];
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bpp = 16;
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break;
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default:
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/* Unsupported at the moment. */
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return;
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}
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/* Resolution */
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width = omap_lcd->width;
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if (width != surface_width(surface) ||
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omap_lcd->height != surface_height(surface)) {
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qemu_console_resize(omap_lcd->con,
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omap_lcd->width, omap_lcd->height);
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surface = qemu_console_surface(omap_lcd->con);
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omap_lcd->invalidate = 1;
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}
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if (omap_lcd->dma->current_frame == 0)
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size = omap_lcd->dma->src_f1_bottom - omap_lcd->dma->src_f1_top;
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else
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size = omap_lcd->dma->src_f2_bottom - omap_lcd->dma->src_f2_top;
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if (frame_offset + ((width * omap_lcd->height * bpp) >> 3) > size + 2) {
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omap_lcd->sync_error = 1;
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omap_lcd_interrupts(omap_lcd);
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omap_lcd->enable = 0;
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return;
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}
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/* Content */
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frame_base = omap_lcd->dma->phys_framebuffer[
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omap_lcd->dma->current_frame] + frame_offset;
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omap_lcd->dma->condition |= 1 << omap_lcd->dma->current_frame;
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if (omap_lcd->dma->interrupts & 1)
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qemu_irq_raise(omap_lcd->dma->irq);
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if (omap_lcd->dma->dual)
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omap_lcd->dma->current_frame ^= 1;
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if (!surface_bits_per_pixel(surface)) {
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return;
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}
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first = 0;
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height = omap_lcd->height;
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if (omap_lcd->subpanel & (1 << 31)) {
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if (omap_lcd->subpanel & (1 << 29))
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first = (omap_lcd->subpanel >> 16) & 0x3ff;
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else
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height = (omap_lcd->subpanel >> 16) & 0x3ff;
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/* TODO: fill the rest of the panel with DPD */
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}
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step = width * bpp >> 3;
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linesize = surface_stride(surface);
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framebuffer_update_display(surface, omap_lcd->sysmem,
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frame_base, width, height,
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step, linesize, 0,
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omap_lcd->invalidate,
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draw_line, omap_lcd->palette,
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&first, &last);
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if (first >= 0) {
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dpy_gfx_update(omap_lcd->con, 0, first, width, last - first + 1);
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}
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omap_lcd->invalidate = 0;
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}
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static void omap_invalidate_display(void *opaque) {
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struct omap_lcd_panel_s *omap_lcd = opaque;
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omap_lcd->invalidate = 1;
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}
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static void omap_lcd_update(struct omap_lcd_panel_s *s) {
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if (!s->enable) {
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s->dma->current_frame = -1;
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s->sync_error = 0;
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if (s->plm != 1)
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s->frame_done = 1;
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omap_lcd_interrupts(s);
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return;
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}
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if (s->dma->current_frame == -1) {
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s->frame_done = 0;
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s->palette_done = 0;
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s->dma->current_frame = 0;
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}
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if (!s->dma->mpu->port[s->dma->src].addr_valid(s->dma->mpu,
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s->dma->src_f1_top) ||
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!s->dma->mpu->port[
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s->dma->src].addr_valid(s->dma->mpu,
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s->dma->src_f1_bottom) ||
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(s->dma->dual &&
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(!s->dma->mpu->port[
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s->dma->src].addr_valid(s->dma->mpu,
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s->dma->src_f2_top) ||
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!s->dma->mpu->port[
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s->dma->src].addr_valid(s->dma->mpu,
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s->dma->src_f2_bottom)))) {
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s->dma->condition |= 1 << 2;
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if (s->dma->interrupts & (1 << 1))
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qemu_irq_raise(s->dma->irq);
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s->enable = 0;
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return;
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}
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s->dma->phys_framebuffer[0] = s->dma->src_f1_top;
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s->dma->phys_framebuffer[1] = s->dma->src_f2_top;
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if (s->plm != 2 && !s->palette_done) {
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cpu_physical_memory_read(
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s->dma->phys_framebuffer[s->dma->current_frame],
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(void *)s->palette, 0x200);
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s->palette_done = 1;
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omap_lcd_interrupts(s);
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}
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}
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static uint64_t omap_lcdc_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *) opaque;
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switch (addr) {
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case 0x00: /* LCD_CONTROL */
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return (s->tft << 23) | (s->plm << 20) |
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(s->tft << 7) | (s->interrupts << 3) |
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(s->mono << 1) | s->enable | s->ctrl | 0xfe000c34;
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case 0x04: /* LCD_TIMING0 */
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return (s->timing[0] << 10) | (s->width - 1) | 0x0000000f;
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case 0x08: /* LCD_TIMING1 */
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return (s->timing[1] << 10) | (s->height - 1);
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case 0x0c: /* LCD_TIMING2 */
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return s->timing[2] | 0xfc000000;
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case 0x10: /* LCD_STATUS */
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return (s->palette_done << 6) | (s->sync_error << 2) | s->frame_done;
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case 0x14: /* LCD_SUBPANEL */
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return s->subpanel;
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default:
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break;
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}
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OMAP_BAD_REG(addr);
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return 0;
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}
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static void omap_lcdc_write(void *opaque, hwaddr addr,
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uint64_t value, unsigned size)
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{
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struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *) opaque;
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switch (addr) {
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case 0x00: /* LCD_CONTROL */
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s->plm = (value >> 20) & 3;
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s->tft = (value >> 7) & 1;
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s->interrupts = (value >> 3) & 3;
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s->mono = (value >> 1) & 1;
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s->ctrl = value & 0x01cff300;
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if (s->enable != (value & 1)) {
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s->enable = value & 1;
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omap_lcd_update(s);
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}
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break;
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case 0x04: /* LCD_TIMING0 */
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s->timing[0] = value >> 10;
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s->width = (value & 0x3ff) + 1;
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break;
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case 0x08: /* LCD_TIMING1 */
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s->timing[1] = value >> 10;
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s->height = (value & 0x3ff) + 1;
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break;
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case 0x0c: /* LCD_TIMING2 */
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s->timing[2] = value;
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break;
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case 0x10: /* LCD_STATUS */
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break;
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case 0x14: /* LCD_SUBPANEL */
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s->subpanel = value & 0xa1ffffff;
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break;
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default:
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OMAP_BAD_REG(addr);
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}
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}
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static const MemoryRegionOps omap_lcdc_ops = {
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.read = omap_lcdc_read,
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.write = omap_lcdc_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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void omap_lcdc_reset(struct omap_lcd_panel_s *s)
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{
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s->dma->current_frame = -1;
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s->plm = 0;
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s->tft = 0;
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s->mono = 0;
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s->enable = 0;
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s->width = 0;
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s->height = 0;
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s->interrupts = 0;
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s->timing[0] = 0;
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s->timing[1] = 0;
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s->timing[2] = 0;
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s->subpanel = 0;
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s->palette_done = 0;
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s->frame_done = 0;
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s->sync_error = 0;
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s->invalidate = 1;
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s->subpanel = 0;
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s->ctrl = 0;
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}
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static const GraphicHwOps omap_ops = {
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.invalidate = omap_invalidate_display,
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.gfx_update = omap_update_display,
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};
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struct omap_lcd_panel_s *omap_lcdc_init(MemoryRegion *sysmem,
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hwaddr base,
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qemu_irq irq,
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struct omap_dma_lcd_channel_s *dma,
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omap_clk clk)
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{
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struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *)
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g_malloc0(sizeof(struct omap_lcd_panel_s));
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s->irq = irq;
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s->dma = dma;
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s->sysmem = sysmem;
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omap_lcdc_reset(s);
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memory_region_init_io(&s->iomem, NULL, &omap_lcdc_ops, s, "omap.lcdc", 0x100);
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memory_region_add_subregion(sysmem, base, &s->iomem);
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s->con = graphic_console_init(NULL, 0, &omap_ops, s);
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return s;
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}
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