mirror_qemu/target/loongarch/insn_trans
Rui Wang b4bda2006f
target/loongarch: Adjust the layout of hardware flags bit fields
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Rui Wang <wangrui@loongson.cn>
Message-Id: <20221104040517.222059-2-wangrui@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
2022-11-04 17:10:52 +08:00
..
trans_arith.c.inc
trans_atomic.c.inc target/loongarch: Add fixed point atomic instruction translation 2022-06-06 18:09:03 +00:00
trans_bit.c.inc target/loongarch: bstrins.w src register need EXT_NONE 2022-10-17 10:28:35 +08:00
trans_branch.c.inc target/loongarch: Add branch instruction translation 2022-06-06 18:09:03 +00:00
trans_extra.c.inc target/loongarch: Add timer related instructions support. 2022-06-06 18:09:03 +00:00
trans_farith.c.inc target/loongarch: Fix fnm{sub/add}_{s/d} set wrong flags 2022-10-17 10:28:35 +08:00
trans_fcmp.c.inc target/loongarch: Add floating point comparison instruction translation 2022-06-06 18:09:03 +00:00
trans_fcnv.c.inc target/loongarch: Add floating point conversion instruction translation 2022-06-06 18:09:03 +00:00
trans_fmemory.c.inc target/loongarch: Add floating point load/store instruction translation 2022-06-06 18:09:03 +00:00
trans_fmov.c.inc target/loongarch: Remove cpu_fcsr0 2022-08-08 19:42:53 -07:00
trans_memory.c.inc target/loongarch: Add fixed point atomic instruction translation 2022-06-06 18:09:03 +00:00
trans_privileged.c.inc target/loongarch: Adjust the layout of hardware flags bit fields 2022-11-04 17:10:52 +08:00
trans_shift.c.inc target/loongarch: Add fixed point shift instruction translation 2022-06-06 18:09:03 +00:00