mirror of https://github.com/proxmox/mirror_qemu
314 lines
11 KiB
C
314 lines
11 KiB
C
#include "hw/hw.h"
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#include "hw/boards.h"
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#include "exec-all.h"
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void register_machines(void)
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{
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qemu_register_machine(&mips_malta_machine);
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qemu_register_machine(&mips_magnum_machine);
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qemu_register_machine(&mips_pica61_machine);
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qemu_register_machine(&mips_mipssim_machine);
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qemu_register_machine(&mips_machine);
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}
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static void save_tc(QEMUFile *f, TCState *tc)
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{
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int i;
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/* Save active TC */
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for(i = 0; i < 32; i++)
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qemu_put_betls(f, &tc->gpr[i]);
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qemu_put_betls(f, &tc->PC);
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for(i = 0; i < MIPS_DSP_ACC; i++)
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qemu_put_betls(f, &tc->HI[i]);
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for(i = 0; i < MIPS_DSP_ACC; i++)
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qemu_put_betls(f, &tc->LO[i]);
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for(i = 0; i < MIPS_DSP_ACC; i++)
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qemu_put_betls(f, &tc->ACX[i]);
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qemu_put_betls(f, &tc->DSPControl);
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qemu_put_sbe32s(f, &tc->CP0_TCStatus);
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qemu_put_sbe32s(f, &tc->CP0_TCBind);
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qemu_put_betls(f, &tc->CP0_TCHalt);
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qemu_put_betls(f, &tc->CP0_TCContext);
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qemu_put_betls(f, &tc->CP0_TCSchedule);
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qemu_put_betls(f, &tc->CP0_TCScheFBack);
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qemu_put_sbe32s(f, &tc->CP0_Debug_tcstatus);
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}
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static void save_fpu(QEMUFile *f, CPUMIPSFPUContext *fpu)
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{
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int i;
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for(i = 0; i < 32; i++)
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qemu_put_be64s(f, &fpu->fpr[i].d);
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qemu_put_s8s(f, &fpu->fp_status.float_detect_tininess);
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qemu_put_s8s(f, &fpu->fp_status.float_rounding_mode);
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qemu_put_s8s(f, &fpu->fp_status.float_exception_flags);
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qemu_put_be32s(f, &fpu->fcr0);
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qemu_put_be32s(f, &fpu->fcr31);
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}
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void cpu_save(QEMUFile *f, void *opaque)
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{
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CPUState *env = opaque;
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int i;
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/* Save active TC */
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save_tc(f, &env->active_tc);
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/* Save active FPU */
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save_fpu(f, &env->active_fpu);
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/* Save MVP */
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qemu_put_sbe32s(f, &env->mvp->CP0_MVPControl);
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qemu_put_sbe32s(f, &env->mvp->CP0_MVPConf0);
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qemu_put_sbe32s(f, &env->mvp->CP0_MVPConf1);
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/* Save TLB */
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qemu_put_be32s(f, &env->tlb->nb_tlb);
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qemu_put_be32s(f, &env->tlb->tlb_in_use);
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for(i = 0; i < MIPS_TLB_MAX; i++) {
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uint16_t flags = ((env->tlb->mmu.r4k.tlb[i].G << 10) |
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(env->tlb->mmu.r4k.tlb[i].C0 << 7) |
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(env->tlb->mmu.r4k.tlb[i].C1 << 4) |
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(env->tlb->mmu.r4k.tlb[i].V0 << 3) |
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(env->tlb->mmu.r4k.tlb[i].V1 << 2) |
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(env->tlb->mmu.r4k.tlb[i].D0 << 1) |
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(env->tlb->mmu.r4k.tlb[i].D1 << 0));
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qemu_put_betls(f, &env->tlb->mmu.r4k.tlb[i].VPN);
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qemu_put_be32s(f, &env->tlb->mmu.r4k.tlb[i].PageMask);
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qemu_put_8s(f, &env->tlb->mmu.r4k.tlb[i].ASID);
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qemu_put_be16s(f, &flags);
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qemu_put_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[0]);
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qemu_put_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[1]);
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}
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/* Save CPU metastate */
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qemu_put_be32s(f, &env->current_tc);
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qemu_put_be32s(f, &env->current_fpu);
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qemu_put_sbe32s(f, &env->error_code);
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qemu_put_be32s(f, &env->hflags);
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qemu_put_betls(f, &env->btarget);
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i = env->bcond;
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qemu_put_sbe32s(f, &i);
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/* Save remaining CP1 registers */
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qemu_put_sbe32s(f, &env->CP0_Index);
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qemu_put_sbe32s(f, &env->CP0_Random);
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qemu_put_sbe32s(f, &env->CP0_VPEControl);
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qemu_put_sbe32s(f, &env->CP0_VPEConf0);
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qemu_put_sbe32s(f, &env->CP0_VPEConf1);
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qemu_put_betls(f, &env->CP0_YQMask);
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qemu_put_betls(f, &env->CP0_VPESchedule);
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qemu_put_betls(f, &env->CP0_VPEScheFBack);
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qemu_put_sbe32s(f, &env->CP0_VPEOpt);
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qemu_put_betls(f, &env->CP0_EntryLo0);
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qemu_put_betls(f, &env->CP0_EntryLo1);
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qemu_put_betls(f, &env->CP0_Context);
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qemu_put_sbe32s(f, &env->CP0_PageMask);
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qemu_put_sbe32s(f, &env->CP0_PageGrain);
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qemu_put_sbe32s(f, &env->CP0_Wired);
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qemu_put_sbe32s(f, &env->CP0_SRSConf0);
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qemu_put_sbe32s(f, &env->CP0_SRSConf1);
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qemu_put_sbe32s(f, &env->CP0_SRSConf2);
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qemu_put_sbe32s(f, &env->CP0_SRSConf3);
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qemu_put_sbe32s(f, &env->CP0_SRSConf4);
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qemu_put_sbe32s(f, &env->CP0_HWREna);
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qemu_put_betls(f, &env->CP0_BadVAddr);
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qemu_put_sbe32s(f, &env->CP0_Count);
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qemu_put_betls(f, &env->CP0_EntryHi);
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qemu_put_sbe32s(f, &env->CP0_Compare);
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qemu_put_sbe32s(f, &env->CP0_Status);
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qemu_put_sbe32s(f, &env->CP0_IntCtl);
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qemu_put_sbe32s(f, &env->CP0_SRSCtl);
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qemu_put_sbe32s(f, &env->CP0_SRSMap);
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qemu_put_sbe32s(f, &env->CP0_Cause);
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qemu_put_betls(f, &env->CP0_EPC);
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qemu_put_sbe32s(f, &env->CP0_PRid);
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qemu_put_sbe32s(f, &env->CP0_EBase);
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qemu_put_sbe32s(f, &env->CP0_Config0);
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qemu_put_sbe32s(f, &env->CP0_Config1);
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qemu_put_sbe32s(f, &env->CP0_Config2);
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qemu_put_sbe32s(f, &env->CP0_Config3);
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qemu_put_sbe32s(f, &env->CP0_Config6);
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qemu_put_sbe32s(f, &env->CP0_Config7);
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qemu_put_betls(f, &env->CP0_LLAddr);
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for(i = 0; i < 8; i++)
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qemu_put_betls(f, &env->CP0_WatchLo[i]);
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for(i = 0; i < 8; i++)
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qemu_put_sbe32s(f, &env->CP0_WatchHi[i]);
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qemu_put_betls(f, &env->CP0_XContext);
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qemu_put_sbe32s(f, &env->CP0_Framemask);
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qemu_put_sbe32s(f, &env->CP0_Debug);
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qemu_put_betls(f, &env->CP0_DEPC);
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qemu_put_sbe32s(f, &env->CP0_Performance0);
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qemu_put_sbe32s(f, &env->CP0_TagLo);
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qemu_put_sbe32s(f, &env->CP0_DataLo);
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qemu_put_sbe32s(f, &env->CP0_TagHi);
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qemu_put_sbe32s(f, &env->CP0_DataHi);
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qemu_put_betls(f, &env->CP0_ErrorEPC);
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qemu_put_sbe32s(f, &env->CP0_DESAVE);
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/* Save inactive TC state */
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for (i = 0; i < MIPS_SHADOW_SET_MAX; i++)
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save_tc(f, &env->tcs[i]);
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for (i = 0; i < MIPS_FPU_MAX; i++)
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save_fpu(f, &env->fpus[i]);
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}
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static void load_tc(QEMUFile *f, TCState *tc)
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{
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int i;
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/* Save active TC */
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for(i = 0; i < 32; i++)
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qemu_get_betls(f, &tc->gpr[i]);
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qemu_get_betls(f, &tc->PC);
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for(i = 0; i < MIPS_DSP_ACC; i++)
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qemu_get_betls(f, &tc->HI[i]);
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for(i = 0; i < MIPS_DSP_ACC; i++)
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qemu_get_betls(f, &tc->LO[i]);
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for(i = 0; i < MIPS_DSP_ACC; i++)
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qemu_get_betls(f, &tc->ACX[i]);
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qemu_get_betls(f, &tc->DSPControl);
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qemu_get_sbe32s(f, &tc->CP0_TCStatus);
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qemu_get_sbe32s(f, &tc->CP0_TCBind);
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qemu_get_betls(f, &tc->CP0_TCHalt);
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qemu_get_betls(f, &tc->CP0_TCContext);
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qemu_get_betls(f, &tc->CP0_TCSchedule);
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qemu_get_betls(f, &tc->CP0_TCScheFBack);
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qemu_get_sbe32s(f, &tc->CP0_Debug_tcstatus);
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}
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static void load_fpu(QEMUFile *f, CPUMIPSFPUContext *fpu)
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{
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int i;
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for(i = 0; i < 32; i++)
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qemu_get_be64s(f, &fpu->fpr[i].d);
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qemu_get_s8s(f, &fpu->fp_status.float_detect_tininess);
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qemu_get_s8s(f, &fpu->fp_status.float_rounding_mode);
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qemu_get_s8s(f, &fpu->fp_status.float_exception_flags);
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qemu_get_be32s(f, &fpu->fcr0);
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qemu_get_be32s(f, &fpu->fcr31);
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}
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int cpu_load(QEMUFile *f, void *opaque, int version_id)
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{
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CPUState *env = opaque;
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int i;
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if (version_id != 3)
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return -EINVAL;
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/* Load active TC */
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load_tc(f, &env->active_tc);
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/* Load active FPU */
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load_fpu(f, &env->active_fpu);
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/* Load MVP */
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qemu_get_sbe32s(f, &env->mvp->CP0_MVPControl);
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qemu_get_sbe32s(f, &env->mvp->CP0_MVPConf0);
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qemu_get_sbe32s(f, &env->mvp->CP0_MVPConf1);
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/* Load TLB */
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qemu_get_be32s(f, &env->tlb->nb_tlb);
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qemu_get_be32s(f, &env->tlb->tlb_in_use);
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for(i = 0; i < MIPS_TLB_MAX; i++) {
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uint16_t flags;
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qemu_get_betls(f, &env->tlb->mmu.r4k.tlb[i].VPN);
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qemu_get_be32s(f, &env->tlb->mmu.r4k.tlb[i].PageMask);
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qemu_get_8s(f, &env->tlb->mmu.r4k.tlb[i].ASID);
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qemu_get_be16s(f, &flags);
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env->tlb->mmu.r4k.tlb[i].G = (flags >> 10) & 1;
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env->tlb->mmu.r4k.tlb[i].C0 = (flags >> 7) & 3;
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env->tlb->mmu.r4k.tlb[i].C1 = (flags >> 4) & 3;
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env->tlb->mmu.r4k.tlb[i].V0 = (flags >> 3) & 1;
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env->tlb->mmu.r4k.tlb[i].V1 = (flags >> 2) & 1;
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env->tlb->mmu.r4k.tlb[i].D0 = (flags >> 1) & 1;
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env->tlb->mmu.r4k.tlb[i].D1 = (flags >> 0) & 1;
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qemu_get_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[0]);
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qemu_get_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[1]);
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}
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/* Load CPU metastate */
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qemu_get_be32s(f, &env->current_tc);
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qemu_get_be32s(f, &env->current_fpu);
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qemu_get_sbe32s(f, &env->error_code);
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qemu_get_be32s(f, &env->hflags);
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qemu_get_betls(f, &env->btarget);
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qemu_get_sbe32s(f, &i);
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env->bcond = i;
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/* Load remaining CP1 registers */
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qemu_get_sbe32s(f, &env->CP0_Index);
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qemu_get_sbe32s(f, &env->CP0_Random);
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qemu_get_sbe32s(f, &env->CP0_VPEControl);
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qemu_get_sbe32s(f, &env->CP0_VPEConf0);
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qemu_get_sbe32s(f, &env->CP0_VPEConf1);
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qemu_get_betls(f, &env->CP0_YQMask);
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qemu_get_betls(f, &env->CP0_VPESchedule);
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qemu_get_betls(f, &env->CP0_VPEScheFBack);
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qemu_get_sbe32s(f, &env->CP0_VPEOpt);
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qemu_get_betls(f, &env->CP0_EntryLo0);
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qemu_get_betls(f, &env->CP0_EntryLo1);
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qemu_get_betls(f, &env->CP0_Context);
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qemu_get_sbe32s(f, &env->CP0_PageMask);
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qemu_get_sbe32s(f, &env->CP0_PageGrain);
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qemu_get_sbe32s(f, &env->CP0_Wired);
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qemu_get_sbe32s(f, &env->CP0_SRSConf0);
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qemu_get_sbe32s(f, &env->CP0_SRSConf1);
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qemu_get_sbe32s(f, &env->CP0_SRSConf2);
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qemu_get_sbe32s(f, &env->CP0_SRSConf3);
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qemu_get_sbe32s(f, &env->CP0_SRSConf4);
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qemu_get_sbe32s(f, &env->CP0_HWREna);
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qemu_get_betls(f, &env->CP0_BadVAddr);
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qemu_get_sbe32s(f, &env->CP0_Count);
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qemu_get_betls(f, &env->CP0_EntryHi);
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qemu_get_sbe32s(f, &env->CP0_Compare);
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qemu_get_sbe32s(f, &env->CP0_Status);
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qemu_get_sbe32s(f, &env->CP0_IntCtl);
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qemu_get_sbe32s(f, &env->CP0_SRSCtl);
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qemu_get_sbe32s(f, &env->CP0_SRSMap);
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qemu_get_sbe32s(f, &env->CP0_Cause);
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qemu_get_betls(f, &env->CP0_EPC);
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qemu_get_sbe32s(f, &env->CP0_PRid);
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qemu_get_sbe32s(f, &env->CP0_EBase);
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qemu_get_sbe32s(f, &env->CP0_Config0);
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qemu_get_sbe32s(f, &env->CP0_Config1);
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qemu_get_sbe32s(f, &env->CP0_Config2);
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qemu_get_sbe32s(f, &env->CP0_Config3);
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qemu_get_sbe32s(f, &env->CP0_Config6);
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qemu_get_sbe32s(f, &env->CP0_Config7);
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qemu_get_betls(f, &env->CP0_LLAddr);
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for(i = 0; i < 8; i++)
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qemu_get_betls(f, &env->CP0_WatchLo[i]);
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for(i = 0; i < 8; i++)
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qemu_get_sbe32s(f, &env->CP0_WatchHi[i]);
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qemu_get_betls(f, &env->CP0_XContext);
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qemu_get_sbe32s(f, &env->CP0_Framemask);
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qemu_get_sbe32s(f, &env->CP0_Debug);
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qemu_get_betls(f, &env->CP0_DEPC);
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qemu_get_sbe32s(f, &env->CP0_Performance0);
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qemu_get_sbe32s(f, &env->CP0_TagLo);
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qemu_get_sbe32s(f, &env->CP0_DataLo);
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qemu_get_sbe32s(f, &env->CP0_TagHi);
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qemu_get_sbe32s(f, &env->CP0_DataHi);
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qemu_get_betls(f, &env->CP0_ErrorEPC);
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qemu_get_sbe32s(f, &env->CP0_DESAVE);
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/* Load inactive TC state */
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for (i = 0; i < MIPS_SHADOW_SET_MAX; i++)
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load_tc(f, &env->tcs[i]);
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for (i = 0; i < MIPS_FPU_MAX; i++)
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load_fpu(f, &env->fpus[i]);
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/* XXX: ensure compatiblity for halted bit ? */
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tlb_flush(env, 1);
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return 0;
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}
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