mirror of https://github.com/proxmox/mirror_qemu
733 lines
21 KiB
C
733 lines
21 KiB
C
/*
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* ARM Generic/Distributed Interrupt Controller
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*
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* Copyright (c) 2006-2007 CodeSourcery.
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* Written by Paul Brook
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*
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* This code is licenced under the GPL.
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*/
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/* This file contains implementation code for the RealView EB interrupt
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controller, MPCore distributed interrupt controller and ARMv7-M
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Nested Vectored Interrupt Controller. */
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//#define DEBUG_GIC
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#ifdef DEBUG_GIC
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#define DPRINTF(fmt, ...) \
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do { printf("arm_gic: " fmt , ## __VA_ARGS__); } while (0)
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#else
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#define DPRINTF(fmt, ...) do {} while(0)
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#endif
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#ifdef NVIC
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static const uint8_t gic_id[] =
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{ 0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1 };
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/* The NVIC has 16 internal vectors. However these are not exposed
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through the normal GIC interface. */
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#define GIC_BASE_IRQ 32
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#else
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static const uint8_t gic_id[] =
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{ 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
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#define GIC_BASE_IRQ 0
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#endif
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#define FROM_SYSBUSGIC(type, dev) \
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DO_UPCAST(type, gic, FROM_SYSBUS(gic_state, dev))
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typedef struct gic_irq_state
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{
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/* ??? The documentation seems to imply the enable bits are global, even
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for per-cpu interrupts. This seems strange. */
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unsigned enabled:1;
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unsigned pending:NCPU;
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unsigned active:NCPU;
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unsigned level:NCPU;
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unsigned model:1; /* 0 = N:N, 1 = 1:N */
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unsigned trigger:1; /* nonzero = edge triggered. */
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} gic_irq_state;
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#define ALL_CPU_MASK ((1 << NCPU) - 1)
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#define GIC_SET_ENABLED(irq) s->irq_state[irq].enabled = 1
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#define GIC_CLEAR_ENABLED(irq) s->irq_state[irq].enabled = 0
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#define GIC_TEST_ENABLED(irq) s->irq_state[irq].enabled
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#define GIC_SET_PENDING(irq, cm) s->irq_state[irq].pending |= (cm)
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#define GIC_CLEAR_PENDING(irq, cm) s->irq_state[irq].pending &= ~(cm)
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#define GIC_TEST_PENDING(irq, cm) ((s->irq_state[irq].pending & (cm)) != 0)
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#define GIC_SET_ACTIVE(irq, cm) s->irq_state[irq].active |= (cm)
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#define GIC_CLEAR_ACTIVE(irq, cm) s->irq_state[irq].active &= ~(cm)
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#define GIC_TEST_ACTIVE(irq, cm) ((s->irq_state[irq].active & (cm)) != 0)
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#define GIC_SET_MODEL(irq) s->irq_state[irq].model = 1
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#define GIC_CLEAR_MODEL(irq) s->irq_state[irq].model = 0
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#define GIC_TEST_MODEL(irq) s->irq_state[irq].model
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#define GIC_SET_LEVEL(irq, cm) s->irq_state[irq].level = (cm)
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#define GIC_CLEAR_LEVEL(irq, cm) s->irq_state[irq].level &= ~(cm)
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#define GIC_TEST_LEVEL(irq, cm) ((s->irq_state[irq].level & (cm)) != 0)
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#define GIC_SET_TRIGGER(irq) s->irq_state[irq].trigger = 1
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#define GIC_CLEAR_TRIGGER(irq) s->irq_state[irq].trigger = 0
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#define GIC_TEST_TRIGGER(irq) s->irq_state[irq].trigger
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#define GIC_GET_PRIORITY(irq, cpu) \
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(((irq) < 32) ? s->priority1[irq][cpu] : s->priority2[(irq) - 32])
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#ifdef NVIC
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#define GIC_TARGET(irq) 1
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#else
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#define GIC_TARGET(irq) s->irq_target[irq]
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#endif
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typedef struct gic_state
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{
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SysBusDevice busdev;
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qemu_irq parent_irq[NCPU];
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int enabled;
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int cpu_enabled[NCPU];
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gic_irq_state irq_state[GIC_NIRQ];
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#ifndef NVIC
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int irq_target[GIC_NIRQ];
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#endif
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int priority1[32][NCPU];
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int priority2[GIC_NIRQ - 32];
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int last_active[GIC_NIRQ][NCPU];
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int priority_mask[NCPU];
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int running_irq[NCPU];
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int running_priority[NCPU];
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int current_pending[NCPU];
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int iomemtype;
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} gic_state;
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/* TODO: Many places that call this routine could be optimized. */
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/* Update interrupt status after enabled or pending bits have been changed. */
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static void gic_update(gic_state *s)
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{
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int best_irq;
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int best_prio;
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int irq;
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int level;
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int cpu;
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int cm;
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for (cpu = 0; cpu < NCPU; cpu++) {
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cm = 1 << cpu;
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s->current_pending[cpu] = 1023;
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if (!s->enabled || !s->cpu_enabled[cpu]) {
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qemu_irq_lower(s->parent_irq[cpu]);
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return;
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}
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best_prio = 0x100;
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best_irq = 1023;
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for (irq = 0; irq < GIC_NIRQ; irq++) {
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if (GIC_TEST_ENABLED(irq) && GIC_TEST_PENDING(irq, cm)) {
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if (GIC_GET_PRIORITY(irq, cpu) < best_prio) {
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best_prio = GIC_GET_PRIORITY(irq, cpu);
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best_irq = irq;
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}
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}
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}
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level = 0;
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if (best_prio <= s->priority_mask[cpu]) {
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s->current_pending[cpu] = best_irq;
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if (best_prio < s->running_priority[cpu]) {
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DPRINTF("Raised pending IRQ %d\n", best_irq);
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level = 1;
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}
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}
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qemu_set_irq(s->parent_irq[cpu], level);
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}
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}
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static void __attribute__((unused))
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gic_set_pending_private(gic_state *s, int cpu, int irq)
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{
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int cm = 1 << cpu;
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if (GIC_TEST_PENDING(irq, cm))
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return;
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DPRINTF("Set %d pending cpu %d\n", irq, cpu);
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GIC_SET_PENDING(irq, cm);
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gic_update(s);
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}
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/* Process a change in an external IRQ input. */
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static void gic_set_irq(void *opaque, int irq, int level)
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{
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gic_state *s = (gic_state *)opaque;
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/* The first external input line is internal interrupt 32. */
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irq += 32;
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if (level == GIC_TEST_LEVEL(irq, ALL_CPU_MASK))
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return;
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if (level) {
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GIC_SET_LEVEL(irq, ALL_CPU_MASK);
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if (GIC_TEST_TRIGGER(irq) || GIC_TEST_ENABLED(irq)) {
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DPRINTF("Set %d pending mask %x\n", irq, GIC_TARGET(irq));
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GIC_SET_PENDING(irq, GIC_TARGET(irq));
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}
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} else {
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GIC_CLEAR_LEVEL(irq, ALL_CPU_MASK);
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}
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gic_update(s);
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}
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static void gic_set_running_irq(gic_state *s, int cpu, int irq)
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{
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s->running_irq[cpu] = irq;
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if (irq == 1023) {
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s->running_priority[cpu] = 0x100;
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} else {
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s->running_priority[cpu] = GIC_GET_PRIORITY(irq, cpu);
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}
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gic_update(s);
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}
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static uint32_t gic_acknowledge_irq(gic_state *s, int cpu)
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{
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int new_irq;
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int cm = 1 << cpu;
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new_irq = s->current_pending[cpu];
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if (new_irq == 1023
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|| GIC_GET_PRIORITY(new_irq, cpu) >= s->running_priority[cpu]) {
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DPRINTF("ACK no pending IRQ\n");
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return 1023;
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}
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s->last_active[new_irq][cpu] = s->running_irq[cpu];
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/* Clear pending flags for both level and edge triggered interrupts.
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Level triggered IRQs will be reasserted once they become inactive. */
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GIC_CLEAR_PENDING(new_irq, GIC_TEST_MODEL(new_irq) ? ALL_CPU_MASK : cm);
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gic_set_running_irq(s, cpu, new_irq);
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DPRINTF("ACK %d\n", new_irq);
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return new_irq;
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}
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static void gic_complete_irq(gic_state * s, int cpu, int irq)
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{
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int update = 0;
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int cm = 1 << cpu;
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DPRINTF("EOI %d\n", irq);
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if (s->running_irq[cpu] == 1023)
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return; /* No active IRQ. */
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if (irq != 1023) {
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/* Mark level triggered interrupts as pending if they are still
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raised. */
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if (!GIC_TEST_TRIGGER(irq) && GIC_TEST_ENABLED(irq)
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&& GIC_TEST_LEVEL(irq, cm) && (GIC_TARGET(irq) & cm) != 0) {
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DPRINTF("Set %d pending mask %x\n", irq, cm);
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GIC_SET_PENDING(irq, cm);
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update = 1;
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}
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}
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if (irq != s->running_irq[cpu]) {
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/* Complete an IRQ that is not currently running. */
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int tmp = s->running_irq[cpu];
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while (s->last_active[tmp][cpu] != 1023) {
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if (s->last_active[tmp][cpu] == irq) {
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s->last_active[tmp][cpu] = s->last_active[irq][cpu];
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break;
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}
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tmp = s->last_active[tmp][cpu];
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}
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if (update) {
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gic_update(s);
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}
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} else {
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/* Complete the current running IRQ. */
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gic_set_running_irq(s, cpu, s->last_active[s->running_irq[cpu]][cpu]);
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}
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}
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static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset)
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{
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gic_state *s = (gic_state *)opaque;
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uint32_t res;
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int irq;
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int i;
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int cpu;
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int cm;
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int mask;
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cpu = gic_get_current_cpu();
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cm = 1 << cpu;
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if (offset < 0x100) {
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#ifndef NVIC
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if (offset == 0)
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return s->enabled;
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if (offset == 4)
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return ((GIC_NIRQ / 32) - 1) | ((NCPU - 1) << 5);
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if (offset < 0x08)
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return 0;
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#endif
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goto bad_reg;
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} else if (offset < 0x200) {
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/* Interrupt Set/Clear Enable. */
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if (offset < 0x180)
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irq = (offset - 0x100) * 8;
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else
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irq = (offset - 0x180) * 8;
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irq += GIC_BASE_IRQ;
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if (irq >= GIC_NIRQ)
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goto bad_reg;
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res = 0;
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for (i = 0; i < 8; i++) {
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if (GIC_TEST_ENABLED(irq + i)) {
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res |= (1 << i);
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}
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}
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} else if (offset < 0x300) {
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/* Interrupt Set/Clear Pending. */
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if (offset < 0x280)
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irq = (offset - 0x200) * 8;
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else
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irq = (offset - 0x280) * 8;
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irq += GIC_BASE_IRQ;
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if (irq >= GIC_NIRQ)
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goto bad_reg;
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res = 0;
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mask = (irq < 32) ? cm : ALL_CPU_MASK;
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for (i = 0; i < 8; i++) {
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if (GIC_TEST_PENDING(irq + i, mask)) {
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res |= (1 << i);
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}
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}
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} else if (offset < 0x400) {
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/* Interrupt Active. */
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irq = (offset - 0x300) * 8 + GIC_BASE_IRQ;
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if (irq >= GIC_NIRQ)
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goto bad_reg;
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res = 0;
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mask = (irq < 32) ? cm : ALL_CPU_MASK;
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for (i = 0; i < 8; i++) {
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if (GIC_TEST_ACTIVE(irq + i, mask)) {
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res |= (1 << i);
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}
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}
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} else if (offset < 0x800) {
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/* Interrupt Priority. */
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irq = (offset - 0x400) + GIC_BASE_IRQ;
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if (irq >= GIC_NIRQ)
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goto bad_reg;
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res = GIC_GET_PRIORITY(irq, cpu);
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#ifndef NVIC
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} else if (offset < 0xc00) {
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/* Interrupt CPU Target. */
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irq = (offset - 0x800) + GIC_BASE_IRQ;
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if (irq >= GIC_NIRQ)
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goto bad_reg;
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if (irq >= 29 && irq <= 31) {
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res = cm;
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} else {
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res = GIC_TARGET(irq);
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}
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} else if (offset < 0xf00) {
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/* Interrupt Configuration. */
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irq = (offset - 0xc00) * 2 + GIC_BASE_IRQ;
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if (irq >= GIC_NIRQ)
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goto bad_reg;
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res = 0;
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for (i = 0; i < 4; i++) {
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if (GIC_TEST_MODEL(irq + i))
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res |= (1 << (i * 2));
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if (GIC_TEST_TRIGGER(irq + i))
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res |= (2 << (i * 2));
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}
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#endif
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} else if (offset < 0xfe0) {
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goto bad_reg;
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} else /* offset >= 0xfe0 */ {
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if (offset & 3) {
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res = 0;
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} else {
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res = gic_id[(offset - 0xfe0) >> 2];
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}
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}
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return res;
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bad_reg:
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hw_error("gic_dist_readb: Bad offset %x\n", (int)offset);
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return 0;
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}
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static uint32_t gic_dist_readw(void *opaque, target_phys_addr_t offset)
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{
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uint32_t val;
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val = gic_dist_readb(opaque, offset);
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val |= gic_dist_readb(opaque, offset + 1) << 8;
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return val;
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}
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static uint32_t gic_dist_readl(void *opaque, target_phys_addr_t offset)
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{
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uint32_t val;
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#ifdef NVIC
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gic_state *s = (gic_state *)opaque;
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uint32_t addr;
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addr = offset;
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if (addr < 0x100 || addr > 0xd00)
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return nvic_readl(s, addr);
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#endif
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val = gic_dist_readw(opaque, offset);
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val |= gic_dist_readw(opaque, offset + 2) << 16;
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return val;
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}
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|
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static void gic_dist_writeb(void *opaque, target_phys_addr_t offset,
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uint32_t value)
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{
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gic_state *s = (gic_state *)opaque;
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int irq;
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int i;
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int cpu;
|
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cpu = gic_get_current_cpu();
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if (offset < 0x100) {
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#ifdef NVIC
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goto bad_reg;
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#else
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if (offset == 0) {
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s->enabled = (value & 1);
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DPRINTF("Distribution %sabled\n", s->enabled ? "En" : "Dis");
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} else if (offset < 4) {
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/* ignored. */
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} else {
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goto bad_reg;
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}
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#endif
|
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} else if (offset < 0x180) {
|
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/* Interrupt Set Enable. */
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irq = (offset - 0x100) * 8 + GIC_BASE_IRQ;
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if (irq >= GIC_NIRQ)
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goto bad_reg;
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if (irq < 16)
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value = 0xff;
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for (i = 0; i < 8; i++) {
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if (value & (1 << i)) {
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int mask = (irq < 32) ? (1 << cpu) : GIC_TARGET(irq);
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if (!GIC_TEST_ENABLED(irq + i))
|
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DPRINTF("Enabled IRQ %d\n", irq + i);
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GIC_SET_ENABLED(irq + i);
|
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/* If a raised level triggered IRQ enabled then mark
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is as pending. */
|
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if (GIC_TEST_LEVEL(irq + i, mask)
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&& !GIC_TEST_TRIGGER(irq + i)) {
|
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DPRINTF("Set %d pending mask %x\n", irq + i, mask);
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GIC_SET_PENDING(irq + i, mask);
|
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}
|
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}
|
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}
|
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} else if (offset < 0x200) {
|
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/* Interrupt Clear Enable. */
|
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irq = (offset - 0x180) * 8 + GIC_BASE_IRQ;
|
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if (irq >= GIC_NIRQ)
|
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goto bad_reg;
|
|
if (irq < 16)
|
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value = 0;
|
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for (i = 0; i < 8; i++) {
|
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if (value & (1 << i)) {
|
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if (GIC_TEST_ENABLED(irq + i))
|
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DPRINTF("Disabled IRQ %d\n", irq + i);
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GIC_CLEAR_ENABLED(irq + i);
|
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}
|
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}
|
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} else if (offset < 0x280) {
|
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/* Interrupt Set Pending. */
|
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irq = (offset - 0x200) * 8 + GIC_BASE_IRQ;
|
|
if (irq >= GIC_NIRQ)
|
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goto bad_reg;
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if (irq < 16)
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irq = 0;
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|
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for (i = 0; i < 8; i++) {
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if (value & (1 << i)) {
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GIC_SET_PENDING(irq + i, GIC_TARGET(irq));
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}
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}
|
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} else if (offset < 0x300) {
|
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/* Interrupt Clear Pending. */
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irq = (offset - 0x280) * 8 + GIC_BASE_IRQ;
|
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if (irq >= GIC_NIRQ)
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goto bad_reg;
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for (i = 0; i < 8; i++) {
|
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/* ??? This currently clears the pending bit for all CPUs, even
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for per-CPU interrupts. It's unclear whether this is the
|
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corect behavior. */
|
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if (value & (1 << i)) {
|
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GIC_CLEAR_PENDING(irq + i, ALL_CPU_MASK);
|
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}
|
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}
|
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} else if (offset < 0x400) {
|
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/* Interrupt Active. */
|
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goto bad_reg;
|
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} else if (offset < 0x800) {
|
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/* Interrupt Priority. */
|
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irq = (offset - 0x400) + GIC_BASE_IRQ;
|
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if (irq >= GIC_NIRQ)
|
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goto bad_reg;
|
|
if (irq < 32) {
|
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s->priority1[irq][cpu] = value;
|
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} else {
|
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s->priority2[irq - 32] = value;
|
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}
|
|
#ifndef NVIC
|
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} else if (offset < 0xc00) {
|
|
/* Interrupt CPU Target. */
|
|
irq = (offset - 0x800) + GIC_BASE_IRQ;
|
|
if (irq >= GIC_NIRQ)
|
|
goto bad_reg;
|
|
if (irq < 29)
|
|
value = 0;
|
|
else if (irq < 32)
|
|
value = ALL_CPU_MASK;
|
|
s->irq_target[irq] = value & ALL_CPU_MASK;
|
|
} else if (offset < 0xf00) {
|
|
/* Interrupt Configuration. */
|
|
irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ;
|
|
if (irq >= GIC_NIRQ)
|
|
goto bad_reg;
|
|
if (irq < 32)
|
|
value |= 0xaa;
|
|
for (i = 0; i < 4; i++) {
|
|
if (value & (1 << (i * 2))) {
|
|
GIC_SET_MODEL(irq + i);
|
|
} else {
|
|
GIC_CLEAR_MODEL(irq + i);
|
|
}
|
|
if (value & (2 << (i * 2))) {
|
|
GIC_SET_TRIGGER(irq + i);
|
|
} else {
|
|
GIC_CLEAR_TRIGGER(irq + i);
|
|
}
|
|
}
|
|
#endif
|
|
} else {
|
|
/* 0xf00 is only handled for 32-bit writes. */
|
|
goto bad_reg;
|
|
}
|
|
gic_update(s);
|
|
return;
|
|
bad_reg:
|
|
hw_error("gic_dist_writeb: Bad offset %x\n", (int)offset);
|
|
}
|
|
|
|
static void gic_dist_writew(void *opaque, target_phys_addr_t offset,
|
|
uint32_t value)
|
|
{
|
|
gic_dist_writeb(opaque, offset, value & 0xff);
|
|
gic_dist_writeb(opaque, offset + 1, value >> 8);
|
|
}
|
|
|
|
static void gic_dist_writel(void *opaque, target_phys_addr_t offset,
|
|
uint32_t value)
|
|
{
|
|
gic_state *s = (gic_state *)opaque;
|
|
#ifdef NVIC
|
|
uint32_t addr;
|
|
addr = offset;
|
|
if (addr < 0x100 || (addr > 0xd00 && addr != 0xf00)) {
|
|
nvic_writel(s, addr, value);
|
|
return;
|
|
}
|
|
#endif
|
|
if (offset == 0xf00) {
|
|
int cpu;
|
|
int irq;
|
|
int mask;
|
|
|
|
cpu = gic_get_current_cpu();
|
|
irq = value & 0x3ff;
|
|
switch ((value >> 24) & 3) {
|
|
case 0:
|
|
mask = (value >> 16) & ALL_CPU_MASK;
|
|
break;
|
|
case 1:
|
|
mask = 1 << cpu;
|
|
break;
|
|
case 2:
|
|
mask = ALL_CPU_MASK ^ (1 << cpu);
|
|
break;
|
|
default:
|
|
DPRINTF("Bad Soft Int target filter\n");
|
|
mask = ALL_CPU_MASK;
|
|
break;
|
|
}
|
|
GIC_SET_PENDING(irq, mask);
|
|
gic_update(s);
|
|
return;
|
|
}
|
|
gic_dist_writew(opaque, offset, value & 0xffff);
|
|
gic_dist_writew(opaque, offset + 2, value >> 16);
|
|
}
|
|
|
|
static CPUReadMemoryFunc * const gic_dist_readfn[] = {
|
|
gic_dist_readb,
|
|
gic_dist_readw,
|
|
gic_dist_readl
|
|
};
|
|
|
|
static CPUWriteMemoryFunc * const gic_dist_writefn[] = {
|
|
gic_dist_writeb,
|
|
gic_dist_writew,
|
|
gic_dist_writel
|
|
};
|
|
|
|
#ifndef NVIC
|
|
static uint32_t gic_cpu_read(gic_state *s, int cpu, int offset)
|
|
{
|
|
switch (offset) {
|
|
case 0x00: /* Control */
|
|
return s->cpu_enabled[cpu];
|
|
case 0x04: /* Priority mask */
|
|
return s->priority_mask[cpu];
|
|
case 0x08: /* Binary Point */
|
|
/* ??? Not implemented. */
|
|
return 0;
|
|
case 0x0c: /* Acknowledge */
|
|
return gic_acknowledge_irq(s, cpu);
|
|
case 0x14: /* Runing Priority */
|
|
return s->running_priority[cpu];
|
|
case 0x18: /* Highest Pending Interrupt */
|
|
return s->current_pending[cpu];
|
|
default:
|
|
hw_error("gic_cpu_read: Bad offset %x\n", (int)offset);
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
static void gic_cpu_write(gic_state *s, int cpu, int offset, uint32_t value)
|
|
{
|
|
switch (offset) {
|
|
case 0x00: /* Control */
|
|
s->cpu_enabled[cpu] = (value & 1);
|
|
DPRINTF("CPU %sabled\n", s->cpu_enabled ? "En" : "Dis");
|
|
break;
|
|
case 0x04: /* Priority mask */
|
|
s->priority_mask[cpu] = (value & 0xff);
|
|
break;
|
|
case 0x08: /* Binary Point */
|
|
/* ??? Not implemented. */
|
|
break;
|
|
case 0x10: /* End Of Interrupt */
|
|
return gic_complete_irq(s, cpu, value & 0x3ff);
|
|
default:
|
|
hw_error("gic_cpu_write: Bad offset %x\n", (int)offset);
|
|
return;
|
|
}
|
|
gic_update(s);
|
|
}
|
|
#endif
|
|
|
|
static void gic_reset(gic_state *s)
|
|
{
|
|
int i;
|
|
memset(s->irq_state, 0, GIC_NIRQ * sizeof(gic_irq_state));
|
|
for (i = 0 ; i < NCPU; i++) {
|
|
s->priority_mask[i] = 0xf0;
|
|
s->current_pending[i] = 1023;
|
|
s->running_irq[i] = 1023;
|
|
s->running_priority[i] = 0x100;
|
|
#ifdef NVIC
|
|
/* The NVIC doesn't have per-cpu interfaces, so enable by default. */
|
|
s->cpu_enabled[i] = 1;
|
|
#else
|
|
s->cpu_enabled[i] = 0;
|
|
#endif
|
|
}
|
|
for (i = 0; i < 16; i++) {
|
|
GIC_SET_ENABLED(i);
|
|
GIC_SET_TRIGGER(i);
|
|
}
|
|
#ifdef NVIC
|
|
/* The NVIC is always enabled. */
|
|
s->enabled = 1;
|
|
#else
|
|
s->enabled = 0;
|
|
#endif
|
|
}
|
|
|
|
static void gic_save(QEMUFile *f, void *opaque)
|
|
{
|
|
gic_state *s = (gic_state *)opaque;
|
|
int i;
|
|
int j;
|
|
|
|
qemu_put_be32(f, s->enabled);
|
|
for (i = 0; i < NCPU; i++) {
|
|
qemu_put_be32(f, s->cpu_enabled[i]);
|
|
#ifndef NVIC
|
|
qemu_put_be32(f, s->irq_target[i]);
|
|
#endif
|
|
for (j = 0; j < 32; j++)
|
|
qemu_put_be32(f, s->priority1[j][i]);
|
|
for (j = 0; j < GIC_NIRQ; j++)
|
|
qemu_put_be32(f, s->last_active[j][i]);
|
|
qemu_put_be32(f, s->priority_mask[i]);
|
|
qemu_put_be32(f, s->running_irq[i]);
|
|
qemu_put_be32(f, s->running_priority[i]);
|
|
qemu_put_be32(f, s->current_pending[i]);
|
|
}
|
|
for (i = 0; i < GIC_NIRQ - 32; i++) {
|
|
qemu_put_be32(f, s->priority2[i]);
|
|
}
|
|
for (i = 0; i < GIC_NIRQ; i++) {
|
|
qemu_put_byte(f, s->irq_state[i].enabled);
|
|
qemu_put_byte(f, s->irq_state[i].pending);
|
|
qemu_put_byte(f, s->irq_state[i].active);
|
|
qemu_put_byte(f, s->irq_state[i].level);
|
|
qemu_put_byte(f, s->irq_state[i].model);
|
|
qemu_put_byte(f, s->irq_state[i].trigger);
|
|
}
|
|
}
|
|
|
|
static int gic_load(QEMUFile *f, void *opaque, int version_id)
|
|
{
|
|
gic_state *s = (gic_state *)opaque;
|
|
int i;
|
|
int j;
|
|
|
|
if (version_id != 1)
|
|
return -EINVAL;
|
|
|
|
s->enabled = qemu_get_be32(f);
|
|
for (i = 0; i < NCPU; i++) {
|
|
s->cpu_enabled[i] = qemu_get_be32(f);
|
|
#ifndef NVIC
|
|
s->irq_target[i] = qemu_get_be32(f);
|
|
#endif
|
|
for (j = 0; j < 32; j++)
|
|
s->priority1[j][i] = qemu_get_be32(f);
|
|
for (j = 0; j < GIC_NIRQ; j++)
|
|
s->last_active[j][i] = qemu_get_be32(f);
|
|
s->priority_mask[i] = qemu_get_be32(f);
|
|
s->running_irq[i] = qemu_get_be32(f);
|
|
s->running_priority[i] = qemu_get_be32(f);
|
|
s->current_pending[i] = qemu_get_be32(f);
|
|
}
|
|
for (i = 0; i < GIC_NIRQ - 32; i++) {
|
|
s->priority2[i] = qemu_get_be32(f);
|
|
}
|
|
for (i = 0; i < GIC_NIRQ; i++) {
|
|
s->irq_state[i].enabled = qemu_get_byte(f);
|
|
s->irq_state[i].pending = qemu_get_byte(f);
|
|
s->irq_state[i].active = qemu_get_byte(f);
|
|
s->irq_state[i].level = qemu_get_byte(f);
|
|
s->irq_state[i].model = qemu_get_byte(f);
|
|
s->irq_state[i].trigger = qemu_get_byte(f);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void gic_init(gic_state *s)
|
|
{
|
|
int i;
|
|
|
|
qdev_init_gpio_in(&s->busdev.qdev, gic_set_irq, GIC_NIRQ - 32);
|
|
for (i = 0; i < NCPU; i++) {
|
|
sysbus_init_irq(&s->busdev, &s->parent_irq[i]);
|
|
}
|
|
s->iomemtype = cpu_register_io_memory(gic_dist_readfn,
|
|
gic_dist_writefn, s);
|
|
gic_reset(s);
|
|
register_savevm("arm_gic", -1, 1, gic_save, gic_load, s);
|
|
}
|