Li Zhijian bbe51d6ea3 hw/cxl: Pass CXLComponentState to cache_mem_ops ... cache_mem_ops.{read,write}() interprets opaque as CXLComponentState(cxl_cstate) instead of ComponentRegisters(cregs). Fortunately, cregs is the first member of cxl_cstate, so their values are the same. Fixes: 9e58f52d3f ("hw/cxl/component: Introduce CXL components (8.1.x, 8.2.5)") Reviewed-by: Fan Ni <fan.ni@samsung.com> Signed-off-by: Li Zhijian <lizhijian@fujitsu.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20240126120132.24248-8-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> (cherry picked from commit 729d45a6af) Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>		2024-02-14 21:42:04 +03:00
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Kconfig	hw/cxl/component: Introduce CXL components (8.1.x, 8.2.5)	2022-05-13 06:13:35 -04:00
cxl-cdat.c	cxl/cdat: Fix header sum value in CDAT checksum	2024-02-14 21:40:17 +03:00
cxl-component-utils.c	hw/cxl: Pass CXLComponentState to cache_mem_ops	2024-02-14 21:42:04 +03:00
cxl-device-utils.c	hw/cxl/device: read from register values in mdev_reg_read()	2024-02-14 21:41:31 +03:00
cxl-events.c	hw/cxl/mbox: Split mailbox command payload into separate input and output	2023-11-07 03:39:11 -05:00
cxl-host-stubs.c	pci/pci_expander_bridge: For CXL HB delay the HB register memory region setup.	2022-06-09 19:32:49 -04:00
cxl-host.c	hw/cxl: Support 4 HDM decoders at all levels of topology	2023-10-04 18:15:06 -04:00
cxl-mailbox-utils.c	hw/cxl: spelling fixes: limitaions, potentialy, intialized	2023-11-15 11:09:17 +03:00
meson.build	hw/cxl: Add a switch mailbox CCI function	2023-11-07 03:39:11 -05:00
switch-mailbox-cci.c	hw/cxl: Add a switch mailbox CCI function	2023-11-07 03:39:11 -05:00