37 lines
1.6 KiB
Diff
37 lines
1.6 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Richard Henderson <richard.henderson@linaro.org>
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Date: Fri, 5 May 2023 21:40:49 +0100
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Subject: [PATCH] accel/tcg: Fix atomic_mmu_lookup for reads
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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A copy-paste bug had us looking at the victim cache for writes.
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Cc: qemu-stable@nongnu.org
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Reported-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Fixes: 08dff435e2 ("tcg: Probe the proper permissions for atomic ops")
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Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Message-Id: <20230505204049.352469-1-richard.henderson@linaro.org>
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(cherry-picked from commit 8c313254e61ed47a1bf4a2db714b25cdd94fbcce)
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Signed-off-by: Fiona Ebner <f.ebner@proxmox.com>
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---
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accel/tcg/cputlb.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
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index e984a98dc4..145fba45b2 100644
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--- a/accel/tcg/cputlb.c
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+++ b/accel/tcg/cputlb.c
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@@ -1830,7 +1830,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
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} else /* if (prot & PAGE_READ) */ {
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tlb_addr = tlbe->addr_read;
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if (!tlb_hit(tlb_addr, addr)) {
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- if (!VICTIM_TLB_HIT(addr_write, addr)) {
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+ if (!VICTIM_TLB_HIT(addr_read, addr)) {
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tlb_fill(env_cpu(env), addr, size,
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MMU_DATA_LOAD, mmu_idx, retaddr);
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index = tlb_index(env, mmu_idx, addr);
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