97 lines
4.2 KiB
Diff
97 lines
4.2 KiB
Diff
From 02b34affd75f205f50445217ad28ef28002e0bf0 Mon Sep 17 00:00:00 2001
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From: Sameeh Jubran <sameeh@daynix.com>
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Date: Mon, 22 May 2017 14:26:22 +0300
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Subject: [PATCH 09/23] e1000e: Fix ICR "Other" causes clear logic
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This commit fixes a bug which causes the guest to hang. The bug was
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observed upon a "receive overrun" (bit #6 of the ICR register)
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interrupt which could be triggered post migration in a heavy traffic
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environment. Even though the "receive overrun" bit (#6) is masked out
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by the IMS register (refer to the log below) the driver still receives
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an interrupt as the "receive overrun" bit (#6) causes the "Other" -
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bit #24 of the ICR register - bit to be set as documented below. The
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driver handles the interrupt and clears the "Other" bit (#24) but
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doesn't clear the "receive overrun" bit (#6) which leads to an
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infinite loop. Apparently the Windows driver expects that the "receive
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overrun" bit and other ones - documented below - to be cleared when
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the "Other" bit (#24) is cleared.
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So to sum that up:
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1. Bit #6 of the ICR register is set by heavy traffic
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2. As a results of setting bit #6, bit #24 is set
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3. The driver receives an interrupt for bit 24 (it doesn't receieve an
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interrupt for bit #6 as it is masked out by IMS)
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4. The driver handles and clears the interrupt of bit #24
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5. Bit #6 is still set.
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6. 2 happens all over again
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The Interrupt Cause Read - ICR register:
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The ICR has the "Other" bit - bit #24 - that is set when one or more
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of the following ICR register's bits are set:
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LSC - bit #2, RXO - bit #6, MDAC - bit #9, SRPD - bit #16, ACK - bit
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#17, MNG - bit #18
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This bug can occur with any of these bits depending on the driver's
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behaviour and the way it configures the device. However, trying to
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reproduce it with any bit other than RX0 is challenging and came to
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failure as the drivers don't implement most of these bits, trying to
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reproduce it with LSC (Link Status Change - bit #2) bit didn't succeed
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too as it seems that Windows handles this bit differently.
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Log sample of the storm:
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27563@1494850819.411877:e1000e_irq_pending_interrupts ICR PENDING: 0x1000000 (ICR: 0x815000c2, IMS: 0x1a00004)
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27563@1494850819.411900:e1000e_irq_pending_interrupts ICR PENDING: 0x0 (ICR: 0x815000c2, IMS: 0xa00004)
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27563@1494850819.411915:e1000e_irq_pending_interrupts ICR PENDING: 0x0 (ICR: 0x815000c2, IMS: 0xa00004)
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27563@1494850819.412380:e1000e_irq_pending_interrupts ICR PENDING: 0x0 (ICR: 0x815000c2, IMS: 0xa00004)
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27563@1494850819.412395:e1000e_irq_pending_interrupts ICR PENDING: 0x0 (ICR: 0x815000c2, IMS: 0xa00004)
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27563@1494850819.412436:e1000e_irq_pending_interrupts ICR PENDING: 0x0 (ICR: 0x815000c2, IMS: 0xa00004)
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27563@1494850819.412441:e1000e_irq_pending_interrupts ICR PENDING: 0x0 (ICR: 0x815000c2, IMS: 0xa00004)
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27563@1494850819.412998:e1000e_irq_pending_interrupts ICR PENDING: 0x1000000 (ICR: 0x815000c2, IMS: 0x1a00004)
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* This bug behaviour wasn't observed with the Linux driver.
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This commit solves:
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https://bugzilla.redhat.com/show_bug.cgi?id=1447935
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https://bugzilla.redhat.com/show_bug.cgi?id=1449490
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Cc: qemu-stable@nongnu.org
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Signed-off-by: Sameeh Jubran <sjubran@redhat.com>
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Signed-off-by: Jason Wang <jasowang@redhat.com>
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---
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hw/net/e1000e_core.c | 10 ++++++++--
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1 file changed, 8 insertions(+), 2 deletions(-)
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diff --git a/hw/net/e1000e_core.c b/hw/net/e1000e_core.c
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index 28c5be1506..81405640f0 100644
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--- a/hw/net/e1000e_core.c
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+++ b/hw/net/e1000e_core.c
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@@ -2454,14 +2454,20 @@ e1000e_set_ics(E1000ECore *core, int index, uint32_t val)
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static void
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e1000e_set_icr(E1000ECore *core, int index, uint32_t val)
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{
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+ uint32_t icr = 0;
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if ((core->mac[ICR] & E1000_ICR_ASSERTED) &&
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(core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) {
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trace_e1000e_irq_icr_process_iame();
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e1000e_clear_ims_bits(core, core->mac[IAM]);
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}
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- trace_e1000e_irq_icr_write(val, core->mac[ICR], core->mac[ICR] & ~val);
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- core->mac[ICR] &= ~val;
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+ icr = core->mac[ICR] & ~val;
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+ /* Windows driver expects that the "receive overrun" bit and other
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+ * ones to be cleared when the "Other" bit (#24) is cleared.
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+ */
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+ icr = (val & E1000_ICR_OTHER) ? (icr & ~E1000_ICR_OTHER_CAUSES) : icr;
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+ trace_e1000e_irq_icr_write(val, core->mac[ICR], icr);
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+ core->mac[ICR] = icr;
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e1000e_update_interrupt_state(core);
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}
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--
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2.11.0
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