2013-03-12 04:31:07 +04:00
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/*
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* PowerPC MMU, TLB and BAT emulation helpers for QEMU.
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*
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* Copyright (c) 2003-2007 Jocelyn Mayer
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* Copyright (c) 2013 David Gibson, IBM Corporation
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "cpu.h"
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#include "helper.h"
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#include "sysemu/kvm.h"
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#include "kvm_ppc.h"
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#include "mmu-hash32.h"
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//#define DEBUG_MMU
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#ifdef DEBUG_MMU
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# define LOG_MMU(...) qemu_log(__VA_ARGS__)
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# define LOG_MMU_STATE(env) log_cpu_state((env), 0)
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#else
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# define LOG_MMU(...) do { } while (0)
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# define LOG_MMU_STATE(...) do { } while (0)
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#endif
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#define PTE_PTEM_MASK 0x7FFFFFBF
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#define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B)
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static inline int pte_is_valid_hash32(target_ulong pte0)
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{
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return pte0 & 0x80000000 ? 1 : 0;
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}
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2013-03-12 04:31:08 +04:00
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static int pte_check_hash32(mmu_ctx_t *ctx, target_ulong pte0,
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target_ulong pte1, int h, int rw, int type)
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2013-03-12 04:31:07 +04:00
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{
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target_ulong ptem, mmask;
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int access, ret, pteh, ptev, pp;
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ret = -1;
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/* Check validity and table match */
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ptev = pte_is_valid_hash32(pte0);
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pteh = (pte0 >> 6) & 1;
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if (ptev && h == pteh) {
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/* Check vsid & api */
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ptem = pte0 & PTE_PTEM_MASK;
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mmask = PTE_CHECK_MASK;
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pp = pte1 & 0x00000003;
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if (ptem == ctx->ptem) {
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if (ctx->raddr != (hwaddr)-1ULL) {
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/* all matches should have equal RPN, WIMG & PP */
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if ((ctx->raddr & mmask) != (pte1 & mmask)) {
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qemu_log("Bad RPN/WIMG/PP\n");
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return -3;
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}
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}
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/* Compute access rights */
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access = pp_check(ctx->key, pp, ctx->nx);
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/* Keep the matching PTE informations */
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ctx->raddr = pte1;
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ctx->prot = access;
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ret = check_prot(ctx->prot, rw, type);
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if (ret == 0) {
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/* Access granted */
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LOG_MMU("PTE access granted !\n");
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} else {
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/* Access right violation */
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LOG_MMU("PTE access rejected\n");
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}
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}
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}
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return ret;
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}
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2013-03-12 04:31:08 +04:00
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/* PTE table lookup */
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2013-03-12 04:31:09 +04:00
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static int find_pte32(CPUPPCState *env, mmu_ctx_t *ctx, int h,
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int rw, int type, int target_page_bits)
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2013-03-12 04:31:08 +04:00
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{
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hwaddr pteg_off;
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target_ulong pte0, pte1;
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int i, good = -1;
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int ret, r;
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ret = -1; /* No entry found */
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pteg_off = get_pteg_offset(env, ctx->hash[h], HASH_PTE_SIZE_32);
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for (i = 0; i < 8; i++) {
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if (env->external_htab) {
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pte0 = ldl_p(env->external_htab + pteg_off + (i * 8));
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pte1 = ldl_p(env->external_htab + pteg_off + (i * 8) + 4);
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} else {
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pte0 = ldl_phys(env->htab_base + pteg_off + (i * 8));
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pte1 = ldl_phys(env->htab_base + pteg_off + (i * 8) + 4);
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}
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r = pte_check_hash32(ctx, pte0, pte1, h, rw, type);
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LOG_MMU("Load pte from %08" HWADDR_PRIx " => " TARGET_FMT_lx " "
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TARGET_FMT_lx " %d %d %d " TARGET_FMT_lx "\n",
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pteg_off + (i * 8), pte0, pte1, (int)(pte0 >> 31), h,
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(int)((pte0 >> 6) & 1), ctx->ptem);
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switch (r) {
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case -3:
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/* PTE inconsistency */
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return -1;
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case -2:
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/* Access violation */
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ret = -2;
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good = i;
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break;
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case -1:
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default:
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/* No PTE match */
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break;
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case 0:
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/* access granted */
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/* XXX: we should go on looping to check all PTEs consistency
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* but if we can speed-up the whole thing as the
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* result would be undefined if PTEs are not consistent.
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*/
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ret = 0;
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good = i;
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goto done;
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}
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}
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if (good != -1) {
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done:
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LOG_MMU("found PTE at addr %08" HWADDR_PRIx " prot=%01x ret=%d\n",
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ctx->raddr, ctx->prot, ret);
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/* Update page flags */
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pte1 = ctx->raddr;
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if (pte_update_flags(ctx, &pte1, ret, rw) == 1) {
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if (env->external_htab) {
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stl_p(env->external_htab + pteg_off + (good * 8) + 4,
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pte1);
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} else {
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stl_phys_notdirty(env->htab_base + pteg_off +
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(good * 8) + 4, pte1);
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}
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}
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}
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/* We have a TLB that saves 4K pages, so let's
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* split a huge page to 4k chunks */
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if (target_page_bits != TARGET_PAGE_BITS) {
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ctx->raddr |= (ctx->eaddr & ((1 << target_page_bits) - 1))
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& TARGET_PAGE_MASK;
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}
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return ret;
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}
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2013-03-12 04:31:09 +04:00
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2013-03-12 04:31:11 +04:00
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static int get_segment32(CPUPPCState *env, mmu_ctx_t *ctx,
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target_ulong eaddr, int rw, int type)
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2013-03-12 04:31:09 +04:00
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{
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hwaddr hash;
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target_ulong vsid;
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int ds, pr, target_page_bits;
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int ret, ret2;
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target_ulong sr, pgidx;
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pr = msr_pr;
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ctx->eaddr = eaddr;
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sr = env->sr[eaddr >> 28];
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ctx->key = (((sr & 0x20000000) && (pr != 0)) ||
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((sr & 0x40000000) && (pr == 0))) ? 1 : 0;
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ds = sr & 0x80000000 ? 1 : 0;
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ctx->nx = sr & 0x10000000 ? 1 : 0;
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vsid = sr & 0x00FFFFFF;
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target_page_bits = TARGET_PAGE_BITS;
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LOG_MMU("Check segment v=" TARGET_FMT_lx " %d " TARGET_FMT_lx " nip="
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TARGET_FMT_lx " lr=" TARGET_FMT_lx
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" ir=%d dr=%d pr=%d %d t=%d\n",
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eaddr, (int)(eaddr >> 28), sr, env->nip, env->lr, (int)msr_ir,
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(int)msr_dr, pr != 0 ? 1 : 0, rw, type);
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pgidx = (eaddr & ~SEGMENT_MASK_256M) >> target_page_bits;
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hash = vsid ^ pgidx;
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ctx->ptem = (vsid << 7) | (pgidx >> 10);
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LOG_MMU("pte segment: key=%d ds %d nx %d vsid " TARGET_FMT_lx "\n",
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ctx->key, ds, ctx->nx, vsid);
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ret = -1;
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if (!ds) {
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/* Check if instruction fetch is allowed, if needed */
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if (type != ACCESS_CODE || ctx->nx == 0) {
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/* Page address translation */
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LOG_MMU("htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx
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" hash " TARGET_FMT_plx "\n",
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env->htab_base, env->htab_mask, hash);
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ctx->hash[0] = hash;
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ctx->hash[1] = ~hash;
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/* Initialize real address with an invalid value */
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ctx->raddr = (hwaddr)-1ULL;
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LOG_MMU("0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
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" vsid=" TARGET_FMT_lx " ptem=" TARGET_FMT_lx
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" hash=" TARGET_FMT_plx "\n",
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env->htab_base, env->htab_mask, vsid, ctx->ptem,
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ctx->hash[0]);
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/* Primary table lookup */
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ret = find_pte32(env, ctx, 0, rw, type, target_page_bits);
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if (ret < 0) {
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/* Secondary table lookup */
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LOG_MMU("1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
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" vsid=" TARGET_FMT_lx " api=" TARGET_FMT_lx
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" hash=" TARGET_FMT_plx "\n", env->htab_base,
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env->htab_mask, vsid, ctx->ptem, ctx->hash[1]);
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ret2 = find_pte32(env, ctx, 1, rw, type,
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target_page_bits);
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if (ret2 != -1) {
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ret = ret2;
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}
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}
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#if defined(DUMP_PAGE_TABLES)
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if (qemu_log_enabled()) {
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hwaddr curaddr;
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uint32_t a0, a1, a2, a3;
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qemu_log("Page table: " TARGET_FMT_plx " len " TARGET_FMT_plx
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"\n", sdr, mask + 0x80);
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for (curaddr = sdr; curaddr < (sdr + mask + 0x80);
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curaddr += 16) {
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a0 = ldl_phys(curaddr);
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a1 = ldl_phys(curaddr + 4);
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a2 = ldl_phys(curaddr + 8);
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a3 = ldl_phys(curaddr + 12);
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if (a0 != 0 || a1 != 0 || a2 != 0 || a3 != 0) {
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qemu_log(TARGET_FMT_plx ": %08x %08x %08x %08x\n",
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curaddr, a0, a1, a2, a3);
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}
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}
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}
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#endif
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} else {
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LOG_MMU("No access allowed\n");
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ret = -3;
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}
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} else {
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target_ulong sr;
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LOG_MMU("direct store...\n");
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/* Direct-store segment : absolutely *BUGGY* for now */
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/* Direct-store implies a 32-bit MMU.
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* Check the Segment Register's bus unit ID (BUID).
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*/
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sr = env->sr[eaddr >> 28];
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if ((sr & 0x1FF00000) >> 20 == 0x07f) {
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/* Memory-forced I/O controller interface access */
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/* If T=1 and BUID=x'07F', the 601 performs a memory access
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* to SR[28-31] LA[4-31], bypassing all protection mechanisms.
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*/
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ctx->raddr = ((sr & 0xF) << 28) | (eaddr & 0x0FFFFFFF);
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ctx->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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return 0;
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}
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switch (type) {
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case ACCESS_INT:
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/* Integer load/store : only access allowed */
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break;
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case ACCESS_CODE:
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/* No code fetch is allowed in direct-store areas */
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return -4;
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case ACCESS_FLOAT:
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/* Floating point load/store */
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return -4;
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case ACCESS_RES:
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/* lwarx, ldarx or srwcx. */
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return -4;
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case ACCESS_CACHE:
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/* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
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/* Should make the instruction do no-op.
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* As it already do no-op, it's quite easy :-)
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*/
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ctx->raddr = eaddr;
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return 0;
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case ACCESS_EXT:
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/* eciwx or ecowx */
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return -4;
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default:
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qemu_log("ERROR: instruction should not need "
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"address translation\n");
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return -4;
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}
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if ((rw == 1 || ctx->key != 1) && (rw == 0 || ctx->key != 0)) {
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ctx->raddr = eaddr;
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ret = 2;
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} else {
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ret = -2;
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}
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}
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return ret;
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}
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2013-03-12 04:31:11 +04:00
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2013-03-12 04:31:12 +04:00
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2013-03-12 04:31:13 +04:00
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static int ppc_hash32_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
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target_ulong eaddr, int rw,
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int access_type)
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2013-03-12 04:31:11 +04:00
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{
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bool real_mode = (access_type == ACCESS_CODE && msr_ir == 0)
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|| (access_type != ACCESS_CODE && msr_dr == 0);
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if (real_mode) {
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ctx->raddr = eaddr;
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ctx->prot = PAGE_READ | PAGE_EXEC | PAGE_WRITE;
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return 0;
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} else {
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int ret = -1;
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/* Try to find a BAT */
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if (env->nb_BATs != 0) {
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ret = get_bat(env, ctx, eaddr, rw, access_type);
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}
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if (ret < 0) {
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/* We didn't match any BAT entry or don't have BATs */
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ret = get_segment32(env, ctx, eaddr, rw, access_type);
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}
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return ret;
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}
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}
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2013-03-12 04:31:12 +04:00
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2013-03-12 04:31:13 +04:00
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hwaddr ppc_hash32_get_phys_page_debug(CPUPPCState *env, target_ulong addr)
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{
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mmu_ctx_t ctx;
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if (unlikely(ppc_hash32_get_physical_address(env, &ctx, addr, 0, ACCESS_INT)
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|
|
!= 0)) {
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
return ctx.raddr & TARGET_PAGE_MASK;
|
|
|
|
}
|
|
|
|
|
2013-03-12 04:31:12 +04:00
|
|
|
int ppc_hash32_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw,
|
|
|
|
int mmu_idx)
|
|
|
|
{
|
|
|
|
mmu_ctx_t ctx;
|
|
|
|
int access_type;
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
if (rw == 2) {
|
|
|
|
/* code access */
|
|
|
|
rw = 0;
|
|
|
|
access_type = ACCESS_CODE;
|
|
|
|
} else {
|
|
|
|
/* data access */
|
|
|
|
access_type = env->access_type;
|
|
|
|
}
|
|
|
|
ret = ppc_hash32_get_physical_address(env, &ctx, address, rw, access_type);
|
|
|
|
if (ret == 0) {
|
|
|
|
tlb_set_page(env, address & TARGET_PAGE_MASK,
|
|
|
|
ctx.raddr & TARGET_PAGE_MASK, ctx.prot,
|
|
|
|
mmu_idx, TARGET_PAGE_SIZE);
|
|
|
|
ret = 0;
|
|
|
|
} else if (ret < 0) {
|
|
|
|
LOG_MMU_STATE(env);
|
|
|
|
if (access_type == ACCESS_CODE) {
|
|
|
|
switch (ret) {
|
|
|
|
case -1:
|
|
|
|
/* No matches in page tables or TLB */
|
|
|
|
env->exception_index = POWERPC_EXCP_ISI;
|
|
|
|
env->error_code = 0x40000000;
|
|
|
|
break;
|
|
|
|
case -2:
|
|
|
|
/* Access rights violation */
|
|
|
|
env->exception_index = POWERPC_EXCP_ISI;
|
|
|
|
env->error_code = 0x08000000;
|
|
|
|
break;
|
|
|
|
case -3:
|
|
|
|
/* No execute protection violation */
|
|
|
|
env->exception_index = POWERPC_EXCP_ISI;
|
|
|
|
env->error_code = 0x10000000;
|
|
|
|
break;
|
|
|
|
case -4:
|
|
|
|
/* Direct store exception */
|
|
|
|
/* No code fetch is allowed in direct-store areas */
|
|
|
|
env->exception_index = POWERPC_EXCP_ISI;
|
|
|
|
env->error_code = 0x10000000;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
switch (ret) {
|
|
|
|
case -1:
|
|
|
|
/* No matches in page tables or TLB */
|
|
|
|
env->exception_index = POWERPC_EXCP_DSI;
|
|
|
|
env->error_code = 0;
|
|
|
|
env->spr[SPR_DAR] = address;
|
|
|
|
if (rw == 1) {
|
|
|
|
env->spr[SPR_DSISR] = 0x42000000;
|
|
|
|
} else {
|
|
|
|
env->spr[SPR_DSISR] = 0x40000000;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case -2:
|
|
|
|
/* Access rights violation */
|
|
|
|
env->exception_index = POWERPC_EXCP_DSI;
|
|
|
|
env->error_code = 0;
|
|
|
|
env->spr[SPR_DAR] = address;
|
|
|
|
if (rw == 1) {
|
|
|
|
env->spr[SPR_DSISR] = 0x0A000000;
|
|
|
|
} else {
|
|
|
|
env->spr[SPR_DSISR] = 0x08000000;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case -4:
|
|
|
|
/* Direct store exception */
|
|
|
|
switch (access_type) {
|
|
|
|
case ACCESS_FLOAT:
|
|
|
|
/* Floating point load/store */
|
|
|
|
env->exception_index = POWERPC_EXCP_ALIGN;
|
|
|
|
env->error_code = POWERPC_EXCP_ALIGN_FP;
|
|
|
|
env->spr[SPR_DAR] = address;
|
|
|
|
break;
|
|
|
|
case ACCESS_RES:
|
|
|
|
/* lwarx, ldarx or stwcx. */
|
|
|
|
env->exception_index = POWERPC_EXCP_DSI;
|
|
|
|
env->error_code = 0;
|
|
|
|
env->spr[SPR_DAR] = address;
|
|
|
|
if (rw == 1) {
|
|
|
|
env->spr[SPR_DSISR] = 0x06000000;
|
|
|
|
} else {
|
|
|
|
env->spr[SPR_DSISR] = 0x04000000;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case ACCESS_EXT:
|
|
|
|
/* eciwx or ecowx */
|
|
|
|
env->exception_index = POWERPC_EXCP_DSI;
|
|
|
|
env->error_code = 0;
|
|
|
|
env->spr[SPR_DAR] = address;
|
|
|
|
if (rw == 1) {
|
|
|
|
env->spr[SPR_DSISR] = 0x06100000;
|
|
|
|
} else {
|
|
|
|
env->spr[SPR_DSISR] = 0x04100000;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
printf("DSI: invalid exception (%d)\n", ret);
|
|
|
|
env->exception_index = POWERPC_EXCP_PROGRAM;
|
|
|
|
env->error_code =
|
|
|
|
POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL;
|
|
|
|
env->spr[SPR_DAR] = address;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#if 0
|
|
|
|
printf("%s: set exception to %d %02x\n", __func__,
|
|
|
|
env->exception, env->error_code);
|
|
|
|
#endif
|
|
|
|
ret = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|