mirror of https://github.com/proxmox/mirror_qemu
hw/riscv/sifive_e: Create a SiFive E SoC object
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Michael Clark <mjc@sifive.com>master
parent
2308092b2b
commit
651cd8b7e1
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@ -102,18 +102,12 @@ static void riscv_sifive_e_init(MachineState *machine)
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SiFiveEState *s = g_new0(SiFiveEState, 1);
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MemoryRegion *sys_mem = get_system_memory();
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MemoryRegion *main_mem = g_new(MemoryRegion, 1);
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MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
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MemoryRegion *xip_mem = g_new(MemoryRegion, 1);
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int i;
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/* Initialize SOC */
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object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_HART_ARRAY);
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/* Initialize SoC */
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object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_E_SOC);
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object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
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&error_abort);
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object_property_set_str(OBJECT(&s->soc), SIFIVE_E_CPU, "cpu-type",
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&error_abort);
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object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
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&error_abort);
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object_property_set_bool(OBJECT(&s->soc), true, "realized",
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&error_abort);
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@ -123,6 +117,49 @@ static void riscv_sifive_e_init(MachineState *machine)
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memory_region_add_subregion(sys_mem,
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memmap[SIFIVE_E_DTIM].base, main_mem);
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/* Mask ROM reset vector */
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uint32_t reset_vec[2] = {
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0x204002b7, /* 0x1000: lui t0,0x20400 */
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0x00028067, /* 0x1004: jr t0 */
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};
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/* copy in the reset vector in little_endian byte order */
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for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
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reset_vec[i] = cpu_to_le32(reset_vec[i]);
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}
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rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
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memmap[SIFIVE_E_MROM].base, &address_space_memory);
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if (machine->kernel_filename) {
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load_kernel(machine->kernel_filename);
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}
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}
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static void riscv_sifive_e_soc_init(Object *obj)
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{
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SiFiveESoCState *s = RISCV_E_SOC(obj);
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object_initialize(&s->cpus, sizeof(s->cpus), TYPE_RISCV_HART_ARRAY);
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object_property_add_child(obj, "cpus", OBJECT(&s->cpus),
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&error_abort);
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object_property_set_str(OBJECT(&s->cpus), SIFIVE_E_CPU, "cpu-type",
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&error_abort);
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object_property_set_int(OBJECT(&s->cpus), smp_cpus, "num-harts",
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&error_abort);
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}
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static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp)
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{
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const struct MemmapEntry *memmap = sifive_e_memmap;
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SiFiveESoCState *s = RISCV_E_SOC(dev);
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MemoryRegion *sys_mem = get_system_memory();
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MemoryRegion *xip_mem = g_new(MemoryRegion, 1);
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MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
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object_property_set_bool(OBJECT(&s->cpus), true, "realized",
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&error_abort);
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/* Mask ROM */
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memory_region_init_rom(mask_rom, NULL, "riscv.sifive.e.mrom",
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memmap[SIFIVE_E_MROM].size, &error_fatal);
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@ -171,23 +208,6 @@ static void riscv_sifive_e_init(MachineState *machine)
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memmap[SIFIVE_E_XIP].size, &error_fatal);
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memory_region_set_readonly(xip_mem, true);
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memory_region_add_subregion(sys_mem, memmap[SIFIVE_E_XIP].base, xip_mem);
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/* Mask ROM reset vector */
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uint32_t reset_vec[2] = {
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0x204002b7, /* 0x1000: lui t0,0x20400 */
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0x00028067, /* 0x1004: jr t0 */
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};
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/* copy in the reset vector in little_endian byte order */
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for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
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reset_vec[i] = cpu_to_le32(reset_vec[i]);
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}
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rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
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memmap[SIFIVE_E_MROM].base, &address_space_memory);
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if (machine->kernel_filename) {
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load_kernel(machine->kernel_filename);
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}
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}
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static void riscv_sifive_e_machine_init(MachineClass *mc)
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@ -198,3 +218,27 @@ static void riscv_sifive_e_machine_init(MachineClass *mc)
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}
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DEFINE_MACHINE("sifive_e", riscv_sifive_e_machine_init)
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static void riscv_sifive_e_soc_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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dc->realize = riscv_sifive_e_soc_realize;
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/* Reason: Uses serial_hds in realize function, thus can't be used twice */
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dc->user_creatable = false;
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}
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static const TypeInfo riscv_sifive_e_soc_type_info = {
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.name = TYPE_RISCV_E_SOC,
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.parent = TYPE_DEVICE,
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.instance_size = sizeof(SiFiveESoCState),
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.instance_init = riscv_sifive_e_soc_init,
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.class_init = riscv_sifive_e_soc_class_init,
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};
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static void riscv_sifive_e_soc_register_types(void)
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{
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type_register_static(&riscv_sifive_e_soc_type_info);
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}
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type_init(riscv_sifive_e_soc_register_types)
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@ -19,13 +19,25 @@
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#ifndef HW_SIFIVE_E_H
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#define HW_SIFIVE_E_H
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#define TYPE_RISCV_E_SOC "riscv.sifive.e.soc"
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#define RISCV_E_SOC(obj) \
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OBJECT_CHECK(SiFiveESoCState, (obj), TYPE_RISCV_E_SOC)
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typedef struct SiFiveESoCState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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RISCVHartArrayState cpus;
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DeviceState *plic;
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} SiFiveESoCState;
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typedef struct SiFiveEState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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RISCVHartArrayState soc;
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DeviceState *plic;
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SiFiveESoCState soc;
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} SiFiveEState;
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enum {
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