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target/alpha: optimize gen_cvtlq() using deposit op 

Suggested-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20170718045540.16322-10-f4bug@amsat.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
master
Philippe Mathieu-Daudé 2017-07-18 01:55:39 -03:00 committed by Richard Henderson
parent 08d64e0db0
commit 729028a6e2
1 changed files with 3 additions and 5 deletions
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8
target/alpha/translate.c
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@ -783,11 +783,9 @@ static void gen_cvtlq(TCGv vc, TCGv vb)
/* The arithmetic right shift here, plus the sign-extended mask below
yields a sign-extended result without an explicit ext32s_i64. */
tcg_gen_sari_i64(tmp, vb, 32);
tcg_gen_shri_i64(vc, vb, 29);
tcg_gen_andi_i64(tmp, tmp, (int32_t)0xc0000000);
tcg_gen_andi_i64(vc, vc, 0x3fffffff);
tcg_gen_or_i64(vc, vc, tmp);
tcg_gen_shri_i64(tmp, vb, 29);
tcg_gen_sari_i64(vc, vb, 32);
tcg_gen_deposit_i64(vc, vc, tmp, 0, 30);
tcg_temp_free(tmp);
}