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target/mips: Convert Vr54xx MUL* opcodes to decodetree 

Convert the following Integer Multiply-Accumulate opcodes:

 * MULHI        Multiply and move HI
 * MULHIU       Unsigned multiply and move HI
 * MULS         Multiply, negate, and move LO
 * MULSHI       Multiply, negate, and move HI
 * MULSHIU      Unsigned multiply, negate, and move HI
 * MULSU        Unsigned multiply, negate, and move LO

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210808173018.90960-7-f4bug@amsat.org>
master
Philippe Mathieu-Daudé 2021-07-28 13:25:53 +02:00
parent 5fa38eedbd
commit a5e2932068
3 changed files with 18 additions and 24 deletions
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24
target/mips/tcg/translate.c
View File

@ -298,14 +298,8 @@ enum {
#define MASK_MUL_VR54XX(op) (MASK_SPECIAL(op) | (op & (0x1F << 6)))
enum {
OPC_VR54XX_MULS = (0x03 << 6) | OPC_MULT,
OPC_VR54XX_MULSU = (0x03 << 6) | OPC_MULTU,
OPC_VR54XX_MSAC = (0x07 << 6) | OPC_MULT,
OPC_VR54XX_MSACU = (0x07 << 6) | OPC_MULTU,
OPC_VR54XX_MULHI = (0x09 << 6) | OPC_MULT,
OPC_VR54XX_MULHIU = (0x09 << 6) | OPC_MULTU,
OPC_VR54XX_MULSHI = (0x0B << 6) | OPC_MULT,
OPC_VR54XX_MULSHIU = (0x0B << 6) | OPC_MULTU,
OPC_VR54XX_MSACHI = (0x0F << 6) | OPC_MULT,
OPC_VR54XX_MSACHIU = (0x0F << 6) | OPC_MULTU,
};
@ -3770,30 +3764,12 @@ static void gen_mul_vr54xx(DisasContext *ctx, uint32_t opc,
gen_load_gpr(t1, rt);
switch (opc) {
case OPC_VR54XX_MULS:
gen_helper_muls(t0, cpu_env, t0, t1);
break;
case OPC_VR54XX_MULSU:
gen_helper_mulsu(t0, cpu_env, t0, t1);
break;
case OPC_VR54XX_MSAC:
gen_helper_msac(t0, cpu_env, t0, t1);
break;
case OPC_VR54XX_MSACU:
gen_helper_msacu(t0, cpu_env, t0, t1);
break;
case OPC_VR54XX_MULHI:
gen_helper_mulhi(t0, cpu_env, t0, t1);
break;
case OPC_VR54XX_MULHIU:
gen_helper_mulhiu(t0, cpu_env, t0, t1);
break;
case OPC_VR54XX_MULSHI:
gen_helper_mulshi(t0, cpu_env, t0, t1);
break;
case OPC_VR54XX_MULSHIU:
gen_helper_mulshiu(t0, cpu_env, t0, t1);
break;
case OPC_VR54XX_MSACHI:
gen_helper_msachi(t0, cpu_env, t0, t1);
break;

6
target/mips/tcg/vr54xx.decode
View File

@ -11,7 +11,13 @@
@rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &r
MULS 000000 ..... ..... ..... 00011011000 @rs_rt_rd
MULSU 000000 ..... ..... ..... 00011011001 @rs_rt_rd
MACC 000000 ..... ..... ..... 00101011000 @rs_rt_rd
MACCU 000000 ..... ..... ..... 00101011001 @rs_rt_rd
MULHI 000000 ..... ..... ..... 01001011000 @rs_rt_rd
MULHIU 000000 ..... ..... ..... 01001011001 @rs_rt_rd
MULSHI 000000 ..... ..... ..... 01011011000 @rs_rt_rd
MULSHIU 000000 ..... ..... ..... 01011011001 @rs_rt_rd
MACCHI 000000 ..... ..... ..... 01101011000 @rs_rt_rd
MACCHIU 000000 ..... ..... ..... 01101011001 @rs_rt_rd

12
target/mips/tcg/vr54xx_translate.c
View File

@ -25,6 +25,12 @@
* MACCHI Multiply, accumulate, and move HI
* MACCHIU Unsigned multiply, accumulate, and move HI
* MACCU Unsigned multiply, accumulate, and move LO
* MULHI Multiply and move HI
* MULHIU Unsigned multiply and move HI
* MULS Multiply, negate, and move LO
* MULSHI Multiply, negate, and move HI
* MULSHIU Unsigned multiply, negate, and move HI
* MULSU Unsigned multiply, negate, and move LO
*/
static bool trans_mult_acc(DisasContext *ctx, arg_r *a,
@ -50,3 +56,9 @@ TRANS(MACC, trans_mult_acc, gen_helper_macc);
TRANS(MACCHI, trans_mult_acc, gen_helper_macchi);
TRANS(MACCHIU, trans_mult_acc, gen_helper_macchiu);
TRANS(MACCU, trans_mult_acc, gen_helper_maccu);
TRANS(MULHI, trans_mult_acc, gen_helper_mulhi);
TRANS(MULHIU, trans_mult_acc, gen_helper_mulhiu);
TRANS(MULS, trans_mult_acc, gen_helper_muls);
TRANS(MULSHI, trans_mult_acc, gen_helper_mulshi);
TRANS(MULSHIU, trans_mult_acc, gen_helper_mulshiu);
TRANS(MULSU, trans_mult_acc, gen_helper_mulsu);