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target/mips: Convert Vr54xx MSA* opcodes to decodetree 

Convert the following Integer Multiply-Accumulate opcodes:

 * MSAC         Multiply, negate, accumulate, and move LO
 * MSACHI       Multiply, negate, accumulate, and move HI
 * MSACHIU      Unsigned multiply, negate, accumulate, and move HI
 * MSACU        Unsigned multiply, negate, accumulate, and move LO

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210808173018.90960-8-f4bug@amsat.org>
master
Philippe Mathieu-Daudé 2021-07-28 13:26:10 +02:00
parent a5e2932068
commit bf7720024c
3 changed files with 14 additions and 53 deletions
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55
target/mips/tcg/translate.c
View File

@ -294,16 +294,6 @@ enum {
R6_OPC_SDBBP = 0x0e | OPC_SPECIAL,
};
/* Multiplication variants of the vr54xx. */
#define MASK_MUL_VR54XX(op) (MASK_SPECIAL(op) | (op & (0x1F << 6)))
enum {
OPC_VR54XX_MSAC = (0x07 << 6) | OPC_MULT,
OPC_VR54XX_MSACU = (0x07 << 6) | OPC_MULTU,
OPC_VR54XX_MSACHI = (0x0F << 6) | OPC_MULT,
OPC_VR54XX_MSACHIU = (0x0F << 6) | OPC_MULTU,
};
/* REGIMM (rt field) opcodes */
#define MASK_REGIMM(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 16)))
@ -3754,40 +3744,6 @@ static void gen_mul_txx9(DisasContext *ctx, uint32_t opc,
tcg_temp_free(t1);
}
static void gen_mul_vr54xx(DisasContext *ctx, uint32_t opc,
int rd, int rs, int rt)
{
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
gen_load_gpr(t0, rs);
gen_load_gpr(t1, rt);
switch (opc) {
case OPC_VR54XX_MSAC:
gen_helper_msac(t0, cpu_env, t0, t1);
break;
case OPC_VR54XX_MSACU:
gen_helper_msacu(t0, cpu_env, t0, t1);
break;
case OPC_VR54XX_MSACHI:
gen_helper_msachi(t0, cpu_env, t0, t1);
break;
case OPC_VR54XX_MSACHIU:
gen_helper_msachiu(t0, cpu_env, t0, t1);
break;
default:
MIPS_INVAL("mul vr54xx");
gen_reserved_instruction(ctx);
goto out;
}
gen_store_gpr(t0, rd);
out:
tcg_temp_free(t0);
tcg_temp_free(t1);
}
static void gen_cl(DisasContext *ctx, uint32_t opc,
int rd, int rs)
{
@ -14104,13 +14060,12 @@ static void decode_opc_special_tx79(CPUMIPSState *env, DisasContext *ctx)
static void decode_opc_special_legacy(CPUMIPSState *env, DisasContext *ctx)
{
int rs, rt, rd, sa;
int rs, rt, rd;
uint32_t op1;
rs = (ctx->opcode >> 21) & 0x1f;
rt = (ctx->opcode >> 16) & 0x1f;
rd = (ctx->opcode >> 11) & 0x1f;
sa = (ctx->opcode >> 6) & 0x1f;
op1 = MASK_SPECIAL(ctx->opcode);
switch (op1) {
@ -14140,13 +14095,7 @@ static void decode_opc_special_legacy(CPUMIPSState *env, DisasContext *ctx)
break;
case OPC_MULT:
case OPC_MULTU:
if (sa) {
check_insn(ctx, INSN_VR54XX);
op1 = MASK_MUL_VR54XX(ctx->opcode);
gen_mul_vr54xx(ctx, op1, rd, rs, rt);
} else {
gen_muldiv(ctx, op1, rd & 3, rs, rt);
}
gen_muldiv(ctx, op1, rd & 3, rs, rt);
break;
case OPC_DIV:
case OPC_DIVU:

4
target/mips/tcg/vr54xx.decode
View File

@ -15,9 +15,13 @@ MULS 000000 ..... ..... ..... 00011011000 @rs_rt_rd
MULSU 000000 ..... ..... ..... 00011011001 @rs_rt_rd
MACC 000000 ..... ..... ..... 00101011000 @rs_rt_rd
MACCU 000000 ..... ..... ..... 00101011001 @rs_rt_rd
MSAC 000000 ..... ..... ..... 00111011000 @rs_rt_rd
MSACU 000000 ..... ..... ..... 00111011001 @rs_rt_rd
MULHI 000000 ..... ..... ..... 01001011000 @rs_rt_rd
MULHIU 000000 ..... ..... ..... 01001011001 @rs_rt_rd
MULSHI 000000 ..... ..... ..... 01011011000 @rs_rt_rd
MULSHIU 000000 ..... ..... ..... 01011011001 @rs_rt_rd
MACCHI 000000 ..... ..... ..... 01101011000 @rs_rt_rd
MACCHIU 000000 ..... ..... ..... 01101011001 @rs_rt_rd
MSACHI 000000 ..... ..... ..... 01111011000 @rs_rt_rd
MSACHIU 000000 ..... ..... ..... 01111011001 @rs_rt_rd

8
target/mips/tcg/vr54xx_translate.c
View File

@ -25,6 +25,10 @@
* MACCHI Multiply, accumulate, and move HI
* MACCHIU Unsigned multiply, accumulate, and move HI
* MACCU Unsigned multiply, accumulate, and move LO
* MSAC Multiply, negate, accumulate, and move LO
* MSACHI Multiply, negate, accumulate, and move HI
* MSACHIU Unsigned multiply, negate, accumulate, and move HI
* MSACU Unsigned multiply, negate, accumulate, and move LO
* MULHI Multiply and move HI
* MULHIU Unsigned multiply and move HI
* MULS Multiply, negate, and move LO
@ -56,6 +60,10 @@ TRANS(MACC, trans_mult_acc, gen_helper_macc);
TRANS(MACCHI, trans_mult_acc, gen_helper_macchi);
TRANS(MACCHIU, trans_mult_acc, gen_helper_macchiu);
TRANS(MACCU, trans_mult_acc, gen_helper_maccu);
TRANS(MSAC, trans_mult_acc, gen_helper_msac);
TRANS(MSACHI, trans_mult_acc, gen_helper_msachi);
TRANS(MSACHIU, trans_mult_acc, gen_helper_msachiu);
TRANS(MSACU, trans_mult_acc, gen_helper_msacu);
TRANS(MULHI, trans_mult_acc, gen_helper_mulhi);
TRANS(MULHIU, trans_mult_acc, gen_helper_mulhiu);
TRANS(MULS, trans_mult_acc, gen_helper_muls);